MC68HC08AZ32A Datasheet, PDF (167/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Figure 13-19 shows the port F I/O logic.
READ DDRF ($000D)
WRITE DDRF ($000D)
RESET
WRITE PTF ($0009)
DDRFx
PTFx
Port G
PTFx
READ PTF ($0009)
Figure 13-19. Port F I/O Circuit
When bit DDRFx is a 1, reading address $0009 reads the PTFx data latch. When bit DDRFx is a 0,
reading address $0009 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 13-6 summarizes the operation of the port F pins.
Table 13-6. Port F Pin Functions
DDRF PTF
Bit
Bit
0
X⁽¹⁾
1
X
I/O Pin
Mode
Input, Hi-Z⁽²⁾
Output
Accesses to DDRF
Read/Write
DDRF[6:0]
DDRF[6:0]
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect input.
Accesses to PTF
Read
Write
Pin
PTF[6:0]⁽³⁾
PTF[6:0]
PTF[6:0]
13.8 Port G
Port G is a 3-bit special function port that shares all of its pins with the KBD.
13.8.1 Port G Data Register (PTG)
The port G data register contains a data latch for each of the three port G pins.
Address: $000A
Bit 7
6
Read: 0
0
Write:
Reset:
Alternative Functions:
5
4
3
2
1
Bit 0
0
0
0
PTG2
PTG1
PTG0
Unaffected by reset
KBD2
KBD1
KBD0
= Unimplemented
Figure 13-20. Port G Data Register (PTG)
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
167