MC68HC08AZ32A Datasheet, PDF (75/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Acquisition/Lock Time Specifications
4.9.3 Choosing a Filter Capacitor
As described in 4.9.2 Parametric Influences on Reaction Time, the external filter capacitor, C_F, is critical
to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply
voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference
frequency in mind. For proper operation, the external filter capacitor must be chosen according to this
equation:
C_F
=
C_FA
C
T
⎛
⎜
⎝
f--_C^----V-_G^----D_M^---D--_R^--A--_D^----_V^--_{⎠⎟⎞}
For acceptable values of C_Fact, (see 20.9 CGM Operating Conditions). For the value of V_DDA, choose the
voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the
middle of the range of possible supply values.
This equation does not always yield a commonly available capacitor size, so round to the nearest
available size. If the value is between two different sizes, choose the higher value for better stability.
Choosing the lower size may seem attractive for acquisition time improvement, but the PLL may become
unstable. Also, always choose a capacitor with a tight tolerance (±20% or better) and low dissipation.
4.9.4 Reaction Time Calculation
The actual acquisition and lock times can be calculated using the equations below. These equations yield
nominal values under the following conditions:
• Correct selection of filter capacitor, C_F (see 4.9.3 Choosing a Filter Capacitor).
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters. K_ACQ is the K factor when the PLL
is configured in acquisition mode, and K_TRK is the K factor when the PLL is configured in tracking mode.
(See 4.3.2.2 Acquisition and Tracking Modes).
t_ACQ
=
⎛
⎝
V--f--_{R-D--D-D---V-A-⎠⎞}
⎛
⎝
-K----_A-8--_C---_Q--_⎠⎞
t_AL
=
⎛
⎝
V--f--_{R-D--D-D---V-A-⎠⎞}
⎛
⎝
-K----_T-4--_R---_K--_⎠⎞
t_Lock = t_ACQ + t_AL
NOTE
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the
reference frequency. (See 4.3.2.3 Manual and Automatic PLL Bandwidth Modes). A certain number of
clock cycles, n_ACQ, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆_TRK,
before exiting acquisition mode. A certain number of clock cycles, n_TRK, is required to ascertain that the
PLL is within the lock mode entry tolerance, ∆_Lock. Therefore, the acquisition time, t_ACQ, is an integer
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
75