MC68HC08AZ32A Datasheet, PDF (107/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

LVI Status Register (LVISR)
9.4 LVI Status Register (LVISR)
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-3. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when V_DD falls below the LVI_TRIPF voltage for 32–40 CGMXCLK
cycles. (See Table 9-1). Reset clears the LVIOUT bit.
Table 9-1. LVIOUT Bit Indication
at level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
V_DD
for number of CGMXCLK cycles:
Any
< 32 CGMXCLK cycles
between 32 and 40 CGMXCLK cycles
> 40 CGMXCLK cycles
Any
LVIOUT
0
0
0 or 1
1
Previous value
9.5 LVI Interrupts
The LVI module does not generate interrupt requests.
9.6 Low-Power Modes
The WAIT instruction puts the MCU in low-power consumption standby mode.
9.6.1 Wait Mode
With the LVIPWR bit in the MORA register programmed to 1, the LVI module is active after a WAIT
instruction.
With the LVIRST bit in the MORA register programmed to 1, the LVI module can generate a reset and
bring the MCU out of wait mode.
9.6.2 Stop Mode
With LVISTOP = 1 and LVIPWR = 1 in the MORA register, the LVI module will be active after a STOP
instruction. Because CPU clocks are disabled during stop mode, the LVI trip must bypass the digital filter
to generate a reset and bring the MCU out of stop.
MC68HC08AZ32A Data Sheet, Rev. 2
Freescale Semiconductor
107