MC68HC08AZ32A Datasheet, PDF (222/312 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface (SPI)
16.5.6 Overflow Error
The overflow flag (OVRF) becomes set if the SPI receive data register still has unread data from a
previous transmission when the capture strobe of bit 1 of the next transmission occurs. See Figure 16-5
and Figure 16-6. If an overflow occurs, the data being received is not transferred to the receive data
register so that the unread data can still be read. Therefore, an overflow error always indicates the loss
of data.
OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. MODF and OVRF can generate a receiver/error CPU interrupt request. See Figure 16-10. It is not
possible to enable only MODF or OVRF to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
If an end-of-block transmission interrupt was meant to pull the MCU out of wait, having an overflow
condition without overflow interrupts enabled causes the MCU to hang in wait mode. If the OVRF is
enabled to generate an interrupt, it can pull the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition.
Figure 16-8 shows how it is possible to miss an overflow.
The first part of Figure 16-8 shows how to read the SPSCR and SPDR to clear the SPRF without
problems. However, as illustrated by the second transmission example, the OVRF flag can be set in the
interval between SPSCR and SPDR being read.
In this case, an overflow can easily be missed. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it will not be obvious that bytes are being lost as more transmissions are completed.
To prevent this, the OVRF interrupt should be enabled, or alternatively another read of the SPSCR should
be carried out following the read of the SPDR. This ensures that the OVRF was not set before the SPRF
was cleared and that future transmissions will terminate with an SPRF interrupt. Figure 16-9 illustrates
this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the
ERRIE bit.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
2
5
READ SPDR
3
7
1 BYTE 1 SETS SPRF BIT.
5 CPU READS SPSCR WITH SPRF BIT SET
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.
6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 BYTE 2 SETS SPRF BIT.
7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 16-8. Missed Read of Overflow Condition
MC68HC08AZ32A Data Sheet, Rev. 2
222
Freescale Semiconductor