GX1 Datasheet, PDF (99/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.1.2 Control Registers
The control registers for the GX1 processor use 32 KB of
the memory map, starting at GX_BASE+8000h (see Figure
4-2 on page 98). This area is divided into internal bus inter-
face unit, graphics pipeline, display controller, memory con-
troller, and power management sections:
• The Internal Bus Interface Unit maps 100h locations
starting at GX_BASE+8000h.
• The Graphics Pipeline maps 200h locations starting at
GX_BASE+8100h.
• The Display Controller maps 100h locations starting at
GX_BASE+8300h.
• The Memory Controller maps 100h locations starting at
GX_BASE+8400h
• GX_BASE+8500h-8FFFh is dedicated to power
management registers for the serial packet transmission
control, the user-defined power management address
space, Suspend Refresh, and SMI status for Suspend/
Resume.
The register descriptions are contained in the individual
subsections of this chapter. Accesses to undefined regis-
ters in the GX1 processor control register space will not
cause a hardware error.
4.1.3 Graphics Memory
Graphics memory is allocated from system DRAM by the
system BIOS. The GX1 processor’s graphics memory is
mapped into 4 MB starting at GX_BASE+800000h. This
area includes the frame buffer memory and storage for
internal display controller state. The size of the frame buffer
is a linear map whose size depends on the user’s require-
ments (i.e., resolution, color depth, video buffer, compres-
sion buffer, font caching, etc.). Frame buffer scan lines are
not contiguous in many resolutions, so software that ren-
ders to the frame buffer must use a skip count to advance
between scan lines. The display controller can use the
graphics memory that lies between scan lines for the com-
pression buffer. Accessing graphics memory between the
end of a scan line and the start of another can cause dis-
play problems. The skip count for all supported resolutions
is shown in Table 4-2.
The graphics memory size is programmed by setting the
graphics memory base address in the memory controller
(see Table 4-14 on page 112). Display drivers communi-
cate with system BIOS about resolution changes, to ensure
that the correct amount of graphics memory is allocated.
Since no mechanism exists to recover system DRAM from
the operating system without rebooting when a graphics
resolution change requires an increased amount of graph-
ics memory, the system must be rebooted!
.
Table 4-2. Display Resolution Skip Counts
Screen
Resolution
Pixel
Depth
Skip
Count
640x480
640x480
800x600
800x600
1024x768
1024x768
1280x1024
8 bits
16 bits
8 bits
16 bits
8 bits
16 bits
8 bits
1024
2048
1024
2048
1024
2048
2048
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