GX1 Datasheet, PDF (215/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.1.2.3 s Field (Immediate Data Field Size)
When used, the 1-bit s field determines the size of the
immediate data field. If the s bit is set, the immediate field
of the opcode is 8 bits wide and is sign-extended to match
the operand size of the opcode. See Table 8-6.
Table 8-6. s Field Encoding
Immediate Field Size
s
Field
0 (or not
present)
1
8-Bit
Operand
Size
8 bits
8 bits
16-Bit
Operand Size
16 bits
32-Bit
Operand Size
32 bits
8 bits
(sign-
extended)
8 bits
(sign-
extended)
8.1.2.4 eee Field (MOV-Instruction Register
Selection)
The eee field (bits [5:3]) is used to select the control, debug
and test registers in the MOV instructions. The type of reg-
ister and base registers selected by the eee field are listed
in Table 8-7. The values shown in Table 8-7 are the only valid
encodings for the eee bits.
Table 8-7. eee Field Encoding
eee Field
Register Type
Base Register
000
Control Register
010
Control Register
011
Control Register
100
Control Register
000
Debug Register
001
Debug Register
010
Debug Register
011
Debug Register
110
Debug Register
111
Debug Register
011
Test Register
100
Test Register
101
Test Register
110
Test Register
111
Test Register
CR0
CR2
CR3
CR4
DR0
DR1
DR2
DR3
DR6
DR7
TR3
TR4
TR5
TR6
TR7
8.1.3 mod and r/m Byte (Memory Addressing)
The mod and r/m fields within the mod r/m byte, select the
type of memory addressing to be used. Some instructions
use a fixed addressing mode (e.g., PUSH or POP) and
therefore, these fields are not present. Table 8-8 lists the
addressing method when 16-bit addressing is used and a
mod r/m byte is present. Some mod r/m field encodings are
dependent on the w field and are shown in Table 8-9.
Table 8-8. mod r/m Field Encoding
mod r/m
Field Field
16-Bit Address
Mode with
mod r/m Byte¹
32-Bit Address
Mode with mod r/m
Byte and No s-i-b
Byte Present¹
00
000 DS:[BX+SI]
00
001 DS:[BX+DI]
00
010 SS:[BP+SI]
00
011 SS:[BP+DI]
00
100 DS:[SI]
00
101 DS:[DI]
00
110 DS:[d16]
00
111 DS:[BX]
DS:[EAX]
DS:[ECX]
DS:[EDX]
DS:[EBX]
s-i-b is present
(See Table 8-15)
DS:[d32]
DS:[ESI]
DS:[EDI]
01
000 DS:[BX+SI+d8]
DS:[EAX+d8]
01
001 DS:[BX+DI+d8]
DS:[ECX+d8]
01
010 SS:[BP+SI+d8]
DS:[EDX+d8]
01
011 SS:[BP+DI+d8]
DS:[EBX+d8]
01
100 DS:[SI+d8]
s-i-b is present
(See Table 8-15)
01
101 DS:[DI+d8]
SS:[EBP+d8]
01
110 SS:[BP+d8]
DS:[ESI+d8]
01
111 DS:[BX+d8]
DS:[EDI+d8]
10
000 DS:[BX+SI+d16] DS:[EAX+d32]
10
001 DS:[BX+DI+d16] DS:[ECX+d32]
10
010 SS:[BP+SI+d16] DS:[EDX+d32]
10
011 SS:[BP+DI+d16] DS:[EBX+d32]
10
100 DS:[SI+d16]
s-i-b is present
(See Table 8-15)
10
101 DS:[DI+d16]
SS:[EBP+d32]
10
110 SS:[BP+d16]
DS:[ESI+d32]
10
111 DS:[BX+d16]
DS:[EDI+d32]
11
xxx See Table 8-9.
See Table 8-9
1. d8 refers to 8-bit displacement, d16 refers to 16-bit displace-
ment, and d32 refers to a 32-bit displacement.
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