GX1 Datasheet, PDF (245/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
Table 8-33. Extended MMX Instruction Set Summary
MMX Instructions
Opcode
Operation and Clock Count
PADDSIW Packed Add Signed Word with Saturation Using Implied Destination
MMX Register plus MMX Register to Implied Register 0F51 [11 mm1 mm2] Sum signed packed word from MMX register/memory --->
1
Memory plus MMX Register to Implied Register
0F51 [mod mm r/m] ^{signed packed word in MMX register, saturate, and write result -} 1
--> implied register
PAVEB Packed Average Byte
MMX Register 2 with MMX Register 1
Memory with MMX Register
0F50 [11 mm1 mm2] Average packed byte from the MMX register/memory with
1
0F50 [mod mm r/m] ^{packed byte in the MMX register. Result is placed in the MMX}
1
register.
PDISTIB Packed Distance and Accumulate with Implied Register
Memory, MMX Register to Implied Register
0F54 [mod mm r/m] Find absolute value of difference between packed byte in mem- 2
ory and packed byte in the MMX register. Using unsigned satu-
ration, accumulate with value in implied destination register.
PMACHRIW Packed Multiply and Accumulate with Rounding
Memory to MMX Register
0F5E[mod mm r/m] Multiply the packed word in the MMX register by the packed
2
word in memory. Sum the 32-bit results pairwise. Accumulate
the result with the packed signed word in the implied destination
register.
PMAGW Packed Magnitude
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F52 [11 mm1 mm2] Set the destination equal ---> the packed word with the largest
2
0F52 [mod mm r/m] ^{magnitude, between the packed word in the MMX register/mem-} 2
ory and the MMX register.
PMULHRIW Packed Multiply High with Rounding, Implied Destination
MMX Register 2 to MMX Register1
Memory to MMX Register
0F5D [11 mm1 mm2] Packed multiply high with rounding and store bits 30 - 15 in
2
0F5D [mod mm r/m] ^{implied register.}
2
PMULHRW Packed Multiply High with Rounding
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F59 [11 mm1 mm2] Multiply the signed packed word in the MMX register/memory
2
0F59 [mod mm r/m] ^{with the signed packed word in the MMX register. Round with 1/} 2
2 bit 15, and store bits 30 - 15 of result in the MMX register.
PMVGEZB Packed Conditional Move If Greater Than or Equal to Zero
Memory to MMX Register
0F5C [mod mm r/m] Conditionally move packed byte from memory ---> packed byte 1
in the MMX register if packed byte in implied MMX register is
greater than or equal ---> zero.
PMVLZB Packed Conditional Move If Less Than Zero
Memory to MMX Register
0F5B [mod mm r/m] Conditionally move packed byte from memory ---> packed byte 1
in the MMX register if packed byte in implied MMX register is
less than zero.
PMVNZB Packed Conditional Move If Not Zero
Memory to MMX Register
0F5A [mod mm r/m] Conditionally move packed byte from memory ---> packed byte 1
in the MMX register if packed byte in implied MMX register is not
zero.
PMVZB Packed Conditional Move If Zero
Memory to MMX Register
0F58 [mod mm r/m] Conditionally move packed byte from memory ---> packed byte 1
in the MMX register if packed byte in implied the MMX register is
zero.
PSUBSIW Packed Subtracted with Saturation Using Implied Destination
MMX Register 2 to MMX Register 1
Memory to MMX Register
0F55 [11 mm1 mm2] Subtract signed packed word in the MMX register/memory from 1
0F55 [mod mm r/m] ^{signed packed word in the MMX register, saturate, and write}
1
result ---> implied register.
Revision 1.0
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