GX1 Datasheet, PDF (67/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.5.2.3 Segment Mechanism in Protected Mode
The segment mechanism in protected mode is more com-
plex. Basically as in real and virtual 8086 modes the offset
address is added to the segment base address to produce
a linear address (Figure 3-5). However, the calculation of
the segment base address is based on the contents of
descriptor tables.
If paging is enabled the linear address is further processed
by the paging mechanism.
A more detailed look at the segment mechanisms for real
and virtual 8086 modes and protected modes is illustrated
in Figure 3-6 on page 68. In protected mode, the segment
selector is cached. This is illustrated in Figure 3-7 on page
69.
3.5.2.4 Segment Selectors
The segment registers are used to store segment selec-
tors. In protected mode, the segment selectors are divided
in to three fields: the RPL, TI and INDEX fields as shown in
Figure 3-6 on page 68.
The segments are assigned permission levels to prevent
application program errors from disrupting operating pro-
grams. The Requested Privilege Level (RPL) determines the
effective privilege level of an instruction. RPL = 0 indicates the
most privileged level, and RPL = 3 indicates the least privi-
leged level. Refer to Section 3.9 “Protection” on page 91.
Descriptor tables hold descriptors that allow management
of segments and tables in address space while in protected
mode. The Table Indicator Bit (TI) in the selector selects
either the General Descriptor Table (GDT) or one Local
Descriptor Table (LDT). If TI = 0, GDT is selected; if TI =1,
LDT is selected. The 13-bit INDEX field in the segment
selector is used to index a GDT or LDT.
Offset Mechanism
32 Offset Address
Selector Mechanism
Segment Base
32
Address
Linear
32 _Address
Optional
Paging Mechanism
Physical
32
Memory
Address
Figure 3-5. Protected Mode Address Calculation
Revision 1.0
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