GX1 Datasheet, PDF (87/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.7.5 SMM Instructions
The GX1 processor core automatically saves a minimal
amount of CPU state information when entering SMM which
allows fast SMM service routine entry and exit. After enter-
ing the SMM service routine, the MOV, SVDC, SVLDT and
SVTS instructions can be used to save the complete CPU
state information. If the SMM service routine modifies more
state information than is automatically saved or if it forces
the CPU to power down, the complete CPU state informa-
tion must be saved. Since the CPU is a static device, its
internal state is retained when the input clock is stopped.
Therefore, an entire CPU-state save is not necessary
before stopping the input clock.
The SMM instructions, listed in Table 3-36, can be exe-
cuted only if all the conditions listed below are met.
1) USE_SMI = 1.
2) SMAR size > 0.
3) Current Privilege Level = 0.
4) SMAC bit is high or the CPU is in an SMM service rou-
tine.
If any one of the conditions above is not met and an
attempt is made to execute an SVDC, RSDC, SVLDT,
RSLDT, SVTS, RSTS, or RSM instruction, an invalid
opcode exception is generated. The SMM instructions can
be executed outside of defined SMM space provided the con-
ditions above are met.
The SMINT instruction can be used by software to enter
SMM. The SMINT instruction can only be used outside an
SMM routine if all the conditions listed below are true.
1) USE_SMI = 1
2) SMAR size > 0
3) Current Privilege Level = 0
4) SMAC = 1
If SMI# is asserted to the CPU during a software SMI, the
hardware SMI# is serviced after the software SMI has been
exited by execution of the RSM instruction.
All the SMM instructions (except RSM and SMINT) save or
restore 80 bits of data, allowing the saved values to include
the hidden portion of the register contents.
Table 3-36. SMM Instruction Set
Instruction
Opcode
Format¹
Description
SVDC
RSDC
0F 78h [mod sreg3 r/m] SVDC mem80, sreg3
0F 79h [mod sreg3 r/m] RSDC sreg3, mem80
SVLDT
RSLDT
SVTS
RSTS
SMINT
0F 7Ah [mod 000 r/m] SVLDT mem80
0F 7Bh [mod 000 r/m] RSLDT mem80
0F 7Ch [mod 000 r/m] SVTS mem80
0F 7Dh [mod 000 r/m] RSTS mem80
0F 38h
SMINT
RSM
0F AAh
RSM
1. mem80 = 80-bit memory location.
Save Segment Register and Descriptor:
Saves reg (DS, ES, FS, GS, or SS) to mem80.
Restore Segment Register and Descriptor:
Restores reg (DS, ES, FS, GS, or SS) from mem80. Use RSM
to restore CS.
Processing “RSDC CS, mem80” will produce an exception.
Save LDTR and Descriptor:
Saves Local Descriptor Table (LDTR) to mem80.
Restore LDTR and Descriptor:
Restores Local Descriptor Table (LDTR) from mem80.
Save TSR and Descriptor:
Saves Task State Register (TSR) to mem80.
Restore TSR and Descriptor:
Restores Task State Register (TSR) from mem80.
Software SMM Entry:
CPU enters SMM. CPU state information is saved in SMM
memory space header and execution begins at SMM base
address.
Resume Normal Mode:
Exits SMM. The CPU state is restored using the SMM memory
space header and execution resumes at interrupted point.
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