GX1 Datasheet, PDF (146/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Table 4-29. Display Controller Configuration and Status Registers (Continued)
Bit
Name
Description
15
PXDB
Pixel Double: Allow pixel doubling to stretch the displayed image in the horizontal dimension:
0 = Disable; 1 = Enable.
If bit 15 is enabled, timing parameters should be programmed as if no pixel doubling is used, however, the
frame buffer should be loaded with half the normal pixels per line. Also, the FB_LINE_SIZE parameter in
DC_BUF_SIZE should be set for the number of bytes to be transferred for the line rather than the number
displayed.
14
INTL
Interlace Scan: Allow interlaced scan mode:
0 = Disable (Non-interlaced scanning is supported.)
1 = Enable (If a flat panel is attached, it should be powered down before setting this bit.)
13
PLNR
VGA Planar Mode: This bit must be set high for all VGA planar display modes.
12
FCEN
Flat Panel Center: Allows the border and active portions of a scan line to be qualified as “active” to a flat
panel display via the ENADISP signal. This allows the use of a large border region for centering the flat
panel display. 0 = Disable; 1 = Enable.
When disabled, only the normal active portion of the scan line will be qualified as active.
11
FVSP
Flat Panel Vertical Sync Polarity:
0 = Causes TFT vertical sync signal to be normally low, generating a high pulse during sync interval.
1 = Causes TFT vertical sync signal to be normally high, generating a low pulse during sync interval.
10
FHSP
Flat Panel Horizontal Sync Polarity:
0 = Causes TFT horizontal sync signal to be normally low, generating a high pulse during sync interval.
1 = Causes TFT horizontal sync signal to be normally high, generating a low pulse during sync interval.
9
CVSP
CRT Vertical Sync Polarity:
0 = Causes CRT_VSYNC signal to be normally low, generating a high pulse during the retrace interval.
1 = Cause CRT_VSYNC signal to be normally high, generating a low pulse during the retrace interval.
8
CHSP
CRT Horizontal Sync Polarity:
0 = Causes CRT_HSYNC signal to be normally low, generating a high pulse during the retrace interval.
1 = Causes CRT_HSYNC signal to be normally high, generating a low pulse during the retrace interval.
7
BLNK
Blink Enable: Blink circuitry: 0 = Disable; 1 = Enable.
If enabled, the hardware cursor will blink as well as any pixels. This is provided to maintain compatibility
with VGA text modes. The blink rate is determined by the bit 16 (BKRT).
6
VIEN
Vertical Interrupt Enable: Generate a vertical interrupt on the occurrence of the next vertical sync pulse:
0 = Disable, vertical interrupt is cleared;
1 = Enable.
This bit is provided to maintain backward compatibility with the VGA.
5
TGEN
Timing Generator Enable: Allow timing generator to generate the timing control signals for the display.
0 = Disable, the Timing registers may be reprogrammed, and all circuitry operating on the DCLK will be
reset.
1 = Enable, no write operations are permitted to the Timing registers.
4
DDCK
DDC Clock: This bit is used to provide the serial clock for reading the DDC data pin. This bit is multiplexed
onto the CRT_VSYNC pin, but in order for it to have an effect, the VSYE bit[2] must be set low to disable the
normal vertical sync. Software should then pulse this bit high and low to clock data into the GX1 processor.
This feature is provided to allow support for the VESA Display Data Channel standard level DDC1.
3
BLKE
Blank Enable: Allow generation of the composite blank signal to the display device:
0 = Disable; 1 = Enable.
When disabled, the ENA_DISP output will be a static low level. This allows VESA DPMS compliance.
2
HSYE
Horizontal Sync Enable: Allow generation of the horizontal sync signal to a CRT display device:
0 = Disable; 1 = Enable.
When disabled, the HSYNC output will be a static low level. This allows VESA DPMS compliance.
Note that this bit only applies to the CRT; the flat panel HSYNC is controlled by the automatic power
sequencing logic.
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