GX1 Datasheet, PDF (156/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5.14 CS5530 Display Controller Interface
As previously stated in Section 1.7 “Geode GX1/CS5530
System Designs” on page 13, the GX1 processor inter-
faces with the Geode CS5530 I/O companion chip. This
section will discuss the specifics on signal connections
between the two devices with regards to the display con-
troller.
Because the GX1 processor is used in a system with the
CS5530 I/O companion chip, the need for an external
RAMDAC is eliminated. The CS5530 contains the DACs, a
video accelerator engine, and a TFT interface.
A GX1 processor and CS5530-based system supports
both flat panel and CRT configurations. Figure 4-16 shows
the signal connections for both types of systems.
Geode™ GX1
Processor
PCLK
VID_CLK
DCLK
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_RDY
VID_DATA[7:0]
PIXEL[17:12] (R)
PIXEL[11:6] (G)
PIXEL[5:0] (B)
VID_VAL
CRT_HSYNC
CRT_VSYNC
Flat Panel
Configuration
FP_ENA_VDD
FP_ENA_BKL
FP_DISP_ENA_OUT
PCLK
VID_CLK
DCLK
FP_HSYNC
FP_VSYNC
DISP_ENA
VID_RDY
VID_DATA[7:0]
PIXEL[23:18]
PIXEL[15:10]
PIXEL[7:2]
VID_VAL
HSYNC
VSYNC
FP_HSYNC
FP_VSYNC
FP_CLK
FP_DATA[17:12]
FP_DATA[11:16]
FP_DATA[5:0]
HSYNC_OUT
VSYNC_OUT
DDC_SCL
DDC_SDA
Geode™ CS5530
I/O Companion
IOUTR
IOUTG
IOUTB
Power
Control
Logic
VDD
12VBKL
ENAB
HSYNC
VSYNC
CLK
TFT
Flat
Panel
R[5:0]
G[5:0]
B[5:0]
Pin 13 Pin 3
Pin 14 Pin 2
Pin 1
VGA
Pin 15 Port
Pin 12
CRT Configuration
Figure 4-16. Display Controller Signal Connections
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