GX1 Datasheet, PDF (140/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5.7 Graphics Memory Map
The GX1 processor supports a maximum of 4 MB of graph-
ics memory and will map it to an address space (see Fig-
ure 4-2 on page 98) higher than the maximum amount of
installed RAM. The graphics memory aperture physically
resides at the top of the installed system RAM. The start
address and size of the graphics memory aperture are pro-
grammable on 512 KB boundaries. Typically, the system
BIOS sets the size and start address of the graphics mem-
ory aperture during the boot process based on the amount
of installed RAM, user defined CMOS settings, hard coded,
etc. The graphics pipeline and display controller address
the graphics memory with a 20-bit offset (address bits
[21:2]) and four byte enables into the graphics memory
aperture. The graphics memory stores several buffers that
are used to generate the display: the frame buffer, com-
pressed display buffer, VGA memory, and cursor pat-
tern(s). Any remaining off-screen memory within the
graphics aperture may be used by the display driver as
desired or not at all.
4.5.7.1 DC Memory Organization Registers
The display controller contains a number of registers that
allow full programmability of the graphics memory organi-
zation. This includes starting offsets for each of the buffer
regions described above, line delta parameters for the
frame buffer and compression buffer, as well as com-
pressed line-buffer size information. The starting offsets for
the various buffers are programmable for a high degree of
flexibility in memory organization.
4.5.7.2 Frame Buffer and Compression Buffer Orga-
nization
The GX1 processor supports primary display modes
640x480, 800x600, and 1024x768 at both 8-bpp and 16-
bpp, and 1280x1024 at 8-bpp. Pixels are packed into
DWORDs as shown in Figure 4-15.
In order to simplify address calculations by the rendering
hardware, the frame buffer is organized in an XY fashion
where the offset is simply a concatenation of the X and Y
pixel addresses. All 8-bpp display modes with the excep-
tion of the 1280x1024 resolution will use a 1024-byte line
delta between the starting offsets of adjacent lines. All 16-
bpp display modes and 1280x1024x8-bpp display modes
will use a 2048-byte line delta between the starting offsets
of adjacent lines. If there is room, the space between the
end of a line and the start of the next line will be filled with
the compressed display data for that line, thus allowing effi-
cient memory utilization. For 1024x768 display modes, the
frame-buffer line size is the same as the line delta, so no
room is left for the compressed display data between lines.
In this case, the compressed display buffer begins at the
end of the frame buffer region and is linearly mapped.
8-bpp up to 1024x768
(0, 0)
(1023,0)
DWORD 0 DWORD 1 _...
16-bpp up to 1024x768
8-bpp up to 1280x1024
(0, 0)
(2047,0)
DWORD 0 DWORD 1 _...
(0, 1023)
(1023, 1023)
(0, 1023)
(2047, 1023)
DWORD
Bit Position
Address
Pixel Org - 8-bpp
Pixel Org - 16-bpp
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
3h
(3,0)
(1,0)
2h
(2,0)
1h
(1,0)
(0,0)
0h
(0,0)
Figure 4-15. Pixel Arrangement Within a DWORD
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