GX1 Datasheet, PDF (216/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
Table 8-9. General Registers Selected by mod r/m
Fields and w Field
16-Bit
Operation
32-Bit
Operation
mod
11
11
11
11
11
11
11
11
r/m
w=0 w=1 w=0 w=1
000
AL
AX
AL
EAX
001
CL
CX
CL
ECX
010
DL
DX
DL
EDX
011
BL
BX
BL
EBX
100
AH
SP
AH
ESP
101
CH
BP
CH
EBP
110
DH
SI
DH
ESI
111
BH
DI
BH
EDI
8.1.4 reg Field
The reg field (Table 8-10) determines which general regis-
ters are to be used. The selected register is dependent on
whether a 16- or 32-bit operation is current and on the
status of the w bit.
Table 8-10. General Registers Selected by reg
Field
16-Bit Operation
32-Bit Operation
reg
w=0
000
AL
001
CL
010
DL
011
BL
100
AH
101
CH
110
DH
111
BH
w=1
AX
CX
DX
BX
SP
BP
SI
DI
w=0
AL
CL
DL
BL
AH
CH
DH
BH
w=1
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
8.1.4.2 sreg3 Field (FS and GS Segment Register
Selection)
The sreg3 field (Table 8-12) is 3-bit field that is similar to
the sreg2 field, but allows use of the FS and GS segment
registers.
Table 8-12. sreg3 Field Encoding
sreg3 Field
Segment Register Selected
000
ES
001
CS
010
SS
011
DS
100
FS
101
GS
110
Undefined
111
Undefined
8.1.5 s-i-b Byte (Scale, Indexing, Base)
The s-i-b fields provide scale factor, indexing and a base
field for address selection. The ss, index and base fields are
described next.
8.1.5.1 ss Field (Scale Selection)
The ss field (Table 8-13) specifies the scale factor used in
the offset mechanism for address calculation. The scale
factor multiplies the index value to provide one of the com-
ponents used to calculate the offset address.
Table 8-13. ss Field Encoding
ss Field
Scale Factor
00
x1
01
x2
01
x4
11
x8
8.1.4.1 sreg2 Field (ES, CS, SS, DS Register
Selection)
The sreg2 field (Table 8-11) is a 2-bit field that allows one
of the four 286-type segment registers to be specified.
Table 8-11. sreg2 Field Encoding
sreg2 Field
Segment Register Selected
00
ES
01
CS
10
SS
11
DS
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