GX1 Datasheet, PDF (123/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.3.7 SDRAM Interface Clocking
The GX1 processor drives the SDCLK to the SDRAMs; one
for each DIMM bank. All the control, data, and address sig-
nals driven by the memory controller are sampled by the
SDRAM at the rising edge of SDCLK. SDCLKOUT is a ref-
erence signal used to generate SDCLKIN. Read data is
sampled by the memory controller at the rising edge of
SDCLKIN.
The delay for SDCLKIN from SDCLKOUT must be
designed so that it lags the SDCLKs at the DRAM by
approximately 1 ns (check application notes for additional
information). The delay should also include the SDCLK
transmission line delay. All four SDCLK traces on the board
should be the same length, so there is no skew between
them. These guidelines allow the memory interface to
operate at a higher performance.
SDCLK[3:0]
SDCLKOUT
Geode™ GX1
Processor
SDCLKIN
SDCLK0
SDCLK1
DIMM
0
Delay
SDCLK2
SDCLK3
DIMM
1
Figure 4-9. SDCLKIN Clocking
Revision 1.0
123
www.national.com