GX1 Datasheet, PDF (81/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.6.4 Interrupt and Exception Priorities
As the CPU executes instructions, it follows a consistent
policy for prioritizing exceptions and hardware interrupts.
The priorities for competing interrupts and exceptions are
listed in Table 3-30. SMM interrupts always take prece-
dence. Debug traps for the previous instruction and next
instructions are handled as the next priority. When NMI and
maskable INTR interrupts are both detected at the same
instruction boundary, the GX1 processor services the NMI
interrupt first.
The CPU checks for exceptions in parallel with instruction
decoding and execution. Several exceptions can result
from a single instruction. However, only one exception is
generated upon each attempt to execute the instruction.
Each exception service routine should make the appropri-
ate corrections to the instruction and then restart the
instruction. In this way, exceptions can be serviced until the
instruction executes properly.
The CPU supports instruction restart after all faults, except
when an instruction causes a task switch to a task whose
Task State Segment (TSS) is partially not present. A TSS
can be partially not present if the TSS is not page aligned
and one of the pages where the TSS resides is not cur-
rently in memory.
Table 3-30. Interrupt and Exception Priorities
Priority
Description
Notes
0
Reset.
Caused by the assertion of RESET.
1
SMM hardware interrupt.
SMM interrupts are caused by SMI# asserted and always have high-
est priority.
2
Debug traps and faults from previous instruction.
Includes single-step trap and data breakpoints specified in the debug
registers.
3
Debug traps for next instruction.
Includes instruction execution breakpoints specified in the debug reg-
isters.
4
Non-maskable hardware interrupt.
Caused by NMI asserted.
5
Maskable hardware interrupt.
Caused by INTR asserted and IF = 1.
6
Faults resulting from fetching the next instruction. Includes segment not present, general protection fault and page fault.
7
Faults resulting from instruction decoding.
Includes illegal opcode, instruction too long, or privilege violation.
8
WAIT instruction and TS = 1 and MP = 1.
Device not available exception generated.
9
ESC instruction and EM = 1 or TS = 1.
Device not available exception generated.
10
Floating point error exception.
Caused by unmasked floating point exception with NE = 1.
11
Segmentation faults (for each memory reference
Includes segment not present, stack fault, and general protection
required by the instruction) that prevent transferring fault.
the entire memory operand.
12
Page Faults that prevent transferring the entire
memory operand.
13
Alignment check fault.
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