GX1 Datasheet, PDF (169/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.7.7 PCI Configuration Space Registers
To access the internal PCI configuration registers of the
GX1 processor, the Configuration Address register
(CONFIG_ADDRESS) must be written as a DWORD using
the format shown in Table 4-42. Any other size will be inter-
preted as an I/O write to Port 0CF8h. Also, when entering
the Configuration Index, only the six most significant bits of
the offset are used, and the two least significant bits must
be 00b.
Table 4-43 summarizes the registers located within the
Configuration Space. The tables that follow, give detailed
register/bit formats.
Table 4-42. Format for Accessing the Internal PCI Configuration Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
Reserved
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Configuration Index 0 0
Index
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh-3Fh
40h
41h
42h
43h
44h
45h-FFh
Table 4-43. PCI Configuration Space Register Summary
Type
Name
RO
Vendor Identification
RO
Device Identification
R/W
PCI Command
R/W
Device Status
RO
Revision Identification
RO
Class Code
RO
Cache Line Size
R/W
Latency Timer
--
Reserved
R/W
PCI Control Function 1
R/W
PCI Control Function 2
--
Reserved
R/W
PCI Arbitration Control 1
R/W
PCI Arbitration Control 2
--
Reserved
Default Value
1078h
0001h
0007h
0280h
00h
060000h
00h
00h
00h
00h
96h
00h
80h
00h
00h
Revision 1.0
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