GX1 Datasheet, PDF (111/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
ACT — The activate command is used to open a row in a
particular bank for a subsequent access. The value on the
BA lines selects the bank, and the address on the MA lines
selects the row. This row remains open for accesses until a
precharge command is issued to that bank. A precharge
command must be issued before opening a different row in
the same bank.
WRT — The write command is used to initiate a burst write
access to an active row. The value on the BA lines select
the component bank, and the address provided by the MA
lines select the starting column location. The memory con-
troller does not perform auto precharge during write opera-
tions. This leaves the page open for subsequent accesses.
Data appearing on the MD lines is written to the DQM logic
level appearing coincident with the data. If the DQM signal
is registered low, the corresponding data will be written to
memory. If the DQM is driven high, the corresponding data
will be ignored, and a write will not be executed to that loca-
tion.
READ — The read command is used to initiate a burst
read access to an active row. The value on the BA lines
select the component bank, and the address provided by
the MA lines select the starting column location. The mem-
ory controller does not perform auto precharge during read
operations. Valid data-out from the starting column address
is available following the CAS latency after the read com-
mand. The DQM signals are asserted low during read
operations.
RFSH — Auto refresh is used during normal operation and
is analogous to the CAS-before-RAS (CBR) refresh in con-
ventional DRAMs. During auto refresh the address bits are
"don’t care". The memory controller precharges all banks
prior to an auto refresh cycle. Auto refresh cycles are
issued approximately 15 µs apart.
The self refresh command is used to retain data in the
SDRAMs even when the rest of the system is powered
down. The self refresh command is similar to an auto
refresh command except CKE is disabled (low). The mem-
ory controller issues a self refresh command during 3V
Suspend mode when all the internal clocks are stopped.
4.3.3.1 SDRAM Initialization Sequence
After the clocks have started and stabilized, the memory
controller SDRAM initialization sequence begins:
1) Precharge all component banks
2) Perform eight refresh cycles
3) Perform an MRS cycle
4) Perform eight refresh cycles
This sequence is compatible with the majority of SDRAMs
available from the various vendors.
Revision 1.0
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