GX1 Datasheet, PDF (134/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5 DISPLAY CONTROLLER
The GX1 processor incorporates a display controller that
retrieves display data from the memory controller and for-
mats it for output on a variety of display devices. The GX1
processor connects directly to the graphics Geode I/O
companion. The display controller includes a display FIFO,
compression/decompression (codec) hardware, hardware
cursor, a 256-entry-by-18-bit palette RAM (plus three
extension colors), display timing generator, dither and
frame-rate-modulation circuitry for TFT panels, and versa-
tile output formatting logic. A diagram of the display control-
ler subsystem is shown in Figure 4-14.
Memory ³²
Data
Compressed
32
Line Buffer
(64x32 bit)
Display 64
FIFO
(64x64 bit)
Codec
Cursor
Latch
16
8
Extensions
Palette 9
Addr.
2 _Logic
Palette ¹⁸
RAM
(264x18
bit)
18
Dither
and
FRM
Pseudo/True
Color Mux
8
Output
Format ¹⁸
Video
Graphics
9
Memory
20
Address
Memory
Address
Generator
Control Registers
and
Control Logic
Timing
Generator
Figure 4-14. Display Controller Block Diagram
Output
Control
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