GX1 Datasheet, PDF (50/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.3.2.2 Configuration Registers
The Configuration Registers listed in Table 3-9 are CPU
registers and are selected by register index numbers. The
registers are accessed through I/O memory locations 22h
and 23h. Registers are selected for access by writing an
index number to I/O Port 22h using an OUT instruction
prior to transferring data through I/O Port 23h. This opera-
tion must be atomic. The CLI instruction must be executed
prior to accessing any of these registers.
Each data transfer through I/O Port 23h must be preceded
by a register index selection through I/O Port 22h; other-
wise, subsequent I/O Port 23h operations are directed off-
chip and produce external I/O cycles.
If MAPEN, bit 4 of CCR3 (Index C3h[4]) = 0, external I/O
cycles occur if the register index number is outside the
range C0h-CFh, FEh, and FFh. The MAPEN bit should
remain 0 during normal operation to allow system registers
located at I/O Port 22h to be accessed.
Table 3-9. Configuration Register Summary
Index
Type
Name
Access
Controlled By¹
Default
Value
C1h
R/W
CCR1 — Configuration Control 1
SMI_LOCK
00h
C2h
R/W
CCR2 — Configuration Control 2
--
00h
C3h
R/W
CCR3 — Configuration Control 3
SMI_LOCK
00h
E8h
R/W
CCR4 — Configuration Control 4
MAPEN
85h
EBh
R/W
CCR7 — Configuration Control 7
--
00h
20h
R/W
PCR — Performance Control
MAPEN
07h
B0h
R/W
SMHR0 — SMM Header Address 0
MAPEN
xxh
B1h
R/W
SMHR1 — SMM Header Address 1
MAPEN
xxh
B2h
R/W
SMHR2 — SMM Header Address 2
MAPEN
xxh
B3h
R/W
SMHR3 — SMM Header Address 3
MAPEN
xxh
B8h
R/W
GCR — Graphics Control Register
MAPEN
00h
B9h
R/W
VGACTL — VGA Control Register
--
00h
BAh-BDh
R/W
VGAM0 — VGA Mask Register
--
00h
CDh
R/W
SMAR0 — SMM Address 0
SMI_LOCK
00h
CEh
R/W
SMAR1 — SMM Address 1
SMI_LOCK
00h
CFh
R/W
SMAR2 — SMM Address 2
SMI_LOCK
00h
FEh
RO
DIR0 — Device ID 0
--
4xh
FFh
RO
DIR1 — Device ID 1
--
xxh
1. MAPEN = Index C3h[4] (CCR3) and SMI_LOCK = Index C3h[0] (CCR3).
Reference
(Bit Formats)
Table 3-11 on page 52
Table 3-11 on page 52
Table 3-11 on page 52
Table 3-11 on page 53
Table 3-11 on page 53
Table 3-11 on page 53
Table 3-11 on page 54
Table 3-11 on page 54
Table 3-11 on page 54
Table 3-11 on page 54
Table 4-1 on page 97
Table 4-37 on page 164
Table 4-37 on page 164
Table 3-11 on page 54
Table 3-11 on page 54
Table 3-11 on page 54
Table 3-11 on page 54
Table 3-11 on page 54
www.national.com
50
Revision 1.0