GX1 Datasheet, PDF (41/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

3.0 Processor Programming
This section describes the internal operations of the Geode
GX1 processor from a programmer’s point of view. It
includes a description of the traditional “core” processing
and FPU operations. The integrated function registers are
described at the end of this chapter.
The primary register sets within the processor core include:
• Application Register Set
• System Register Set
• Model Specific Register Set
The initialization of the major registers within the core are
shown in Table 3-1.
The integrated function sets are located in main memory
space and include:
• Internal Bus Interface Unit Register Set
• Graphics Pipeline Register Set
• Display Controller Register Set
• Memory Controller Register Set
• Power Management Register Set
3.1 CORE PROCESSOR INITIALIZATION
The GX1 processor is initialized when the RESET signal is
asserted. The processor is placed in real mode and the
registers listed in Table 3-1 are set to their initialized val-
ues. RESET invalidates and disables the CPU cache, and
turns off paging. When RESET is asserted, the CPU termi-
nates all local bus activity and all internal execution. While
RESET is asserted the internal pipeline is flushed and no
instruction execution or bus activity occurs.
Approximately 150 to 250 external clock cycles after
RESET is deasserted, the processor begins executing
instructions at the top of physical memory (address location
FFFFFFF0h). The actual number of clock cycles depends
on the clock scaling in use. Also, before execution begins,
an additional 2²⁰ clock cycles are needed when self-test is
requested.
Typically, an intersegment jump is placed at FFFFFFF0h.
This instruction will force the processor to begin execution
in the lowest 1 MB of address space.
Table 3-1 lists the core registers and illustrates how they
are initialized.
Register
EAX
EBX
ECX
EDX
EBP
ESI
EDI
ESP
EFLAGS
EIP
ES
CS
SS
DS
FS
GS
IDTR
GDTR
LDTR
TR
CR0
CR2
CR3
CR4
Table 3-1. Initialized Core Register Controls
Register Name
Initialized Contents¹
Comments
Accumulator
Base
Count
Data
Base Pointer
Source Index
Destination Index
Stack Pointer
Extended Flags
Instruction Pointer
Extra Segment
Code Segment
Stack Segment
Data Segment
Extra Segment
Extra Segment
Interrupt Descriptor Table Register
Global Descriptor Table Register
Local Descriptor Table Register
Task Register
Control Register 0
Control Register 2
Control Register 3
Control Register 4
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxx 04 [DIR0]h
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
xxxxxxxxh
00000002h
0000FFF0h
0000h
F000h
0000h
0000h
0000h
0000h
Base = 0, Limit = 3FFh
xxxxxxxxh
xxxxh
xxxxh
60000010h
xxxxxxxxh
xxxxxxxxh
00000000h
00000000h indicates self-test passed.
DIR0 = Device ID
See Table 3-4 on page 46 for bit definitions.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to FFFF0000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
Base address set to 00000000h. Limit set to FFFFh.
See Table 3-7 on page 49 for bit definitions.
See Table 3-7 on page 49 for bit definitions.
See Table 3-7 on page 48 for bit definitions.
See Table 3-7 on page 48 for bit definitions.
Revision 1.0
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