GX1 Datasheet, PDF (59/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.3.2.5 Cache Test Registers
Three test registers are used in testing the processor’s on-
chip cache, TR3-TR5. Table 3-16 is a register map for the
Cache Test Registers with their bit definitions given in Table
3-17 on page 60. The test registers are accessed through
MOV instructions that can be executed only at privilege
level 0 (real mode is always privilege level 0).
The processor’s 16 KB on-chip cache is a four-way set
associative memory that is configured as write-back cache.
Each cache set contains 256 entries. Each entry consists
of a 20-bit tag address, a 16-byte data field, a valid bit, and
four dirty bits.
The 20-bit tag represents the high-order 20 bits of the
physical address. The 16-byte data represents the 16 bytes
of data currently in memory at the physical address repre-
sented by the tag. The valid bit indicates whether the data
bytes in the cache actually contain valid data. The four dirty
bits indicate if the data bytes in the cache have been modi-
fied internally without updating external memory (write-
back configuration). Each dirty bit indicates the status for
one DWORD (4 bytes) within the 16-byte data field.
For each line in the cache, there are three LRU bits that
indicate which of the four sets was most recently accessed.
A line is selected using bits [11:4] of the physical address.
Using a 16-byte cache fill buffer and a 16-byte cache flush
buffer, cache reads and writes may be performed.
Figure 3-1 illustrates the internal cache architecture.
D
E
A11-A4 ^C
O
D
E
Line
Address
255
254
.
.
0
= Cache Entry (153 bits)
Tag Address (20 bits)
Data (128 bits)
Valid Status (1 bit)
Dirty Status (4 bits)
Set 0
Set 1
Set 2
Set 3
LRU
.
.
152---0
.
.
152---0
.
.
152---0
.
.
152---0
.
.
2---0
Figure 3-1. Cache Architecture
Table 3-16. Test Registers for Cache
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR5 Register (R/W)
TR4 Register (R/W)
TR3 Register (R/W)
RSVD
Cache Tag Address
Cache Data
Line Selection
Set/ CTL
DWORD
0
Cache
Dirty Bits
0 00
LRU Bits
Revision 1.0
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