GX1 Datasheet, PDF (39/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Signal Definitions (Continued)
2.2.5 Power, Ground, and No Connect Signals
Signal Name
BGA
Pin No.
SPGA
Pin No.
Type
VSS
Refer to
Table 2-3
(Total of
71)
Refer to
Table 2-5
(Total of
50)
GND
VCC2
Refer to
Table 2-3
(Total of
32)
Refer to
Table 2-5
(Total of
32)
PWR
VCC3
Refer to
Table 2-3
(Total of
32)
Refer to
Table 2-5
(Total of
18)
PWR
NC
AC5
Q5, X2,
Z2,
AM36
Description
Ground Connection
1.6V, 1.8V, or 2.0V (nominal) Core Power Connection
3.3V (nominal) I/O Power Connection
No Connection
A line designated as NC must be left disconnected.
2.2.6 Internal Test and Measurement Signals
Signal Name
BGA
Pin No.
SPGA
Pin No.
Type
FLT#
AC2
AJ3
I
RW_CLK
AE6
AL11
O
TEST[3:0]
TCLK
B22, A23, D28, B32,
O
B21, C21 D26, A33
J2
P4
I
(PU)
(PU)
TDI
D2
F4
I
(PU)
(PU)
TDO
TMS
F1
J1
O
H1
N3
I
(PU)
(PU)
Description
Float
Float forces the GX1 processor to float all outputs in the high-
impedance state and to enter a power-down state.
Raw Clock
This output is the GX1 processor clock. This debug signal can
be used to verify clock operation.
SDRAM Test Outputs
These outputs are used for internal debug only.
Test Clock
JTAG test clock.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
Test Data Input
JTAG serial test-data input.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
Test Data Output
JTAG serial test-data output.
Test Mode Select
JTAG test-mode select.
This pin is internally connected to a weak (>20-kohm) pull-up
resistor.
Revision 1.0
39
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