GX1 Datasheet, PDF (129/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.4.6 Graphics Pipeline Register Descriptions
The graphics pipeline maps 200h locations starting at
GX_BASE+8100h. Refer to Section 4.1.2 “Control Regis-
ters” on page 99 for instructions on accessing these regis-
ters. Table 4-23 summarizes the graphics pipeline registers
and Table 4-24 gives detailed register/bit formats.
GX_BASE+
Memory Offset
8100h-8103h
8104-8107h
8108h-810Bh
810Ch-810Fh
8110h-8113h
8114h-8117h
8120h-8123h
8124h-8127h
8128h-812Bh
812Ch-812Fh
8140h-8143h¹
8144h-8147h¹
8200h-8203h
8204h-8207h
8208h-820Bh
Table 4-23. Graphics Pipeline Configuration Register Summary
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name / Function
GP_DST/START_Y/XCOOR
Destination/Starting Y and X Coordinates Register: In BLT mode this register
specifies the destination Y and X positions for a BLT operation. In Vector mode it
specifies the starting Y and X positions in a vector.
GP_WIDTH/HEIGHT and GP_VECTOR_LENGTH/INIT_ERROR
Width/Height or Vector Length/Initial Error Register: In BLT mode this register
specifies the BLT width and height in pixels. In Vector mode it specifies the vector
initial error and pixel length.
GP_SRC_X/YCOOR and GP_AXIAL/DIAG_ERROR
Source X/Y Coordinate Axial/Diagonal Error Register: In BLT mode this register
specifies the BLT X and Y source. In Vector mode it specifies the axial and diago-
nal error for rendering a vector.
GP_SRC_COLOR_0 and GP_SRC_COLOR_1
Source Color Register: Determines the colors used when expanding mono-
chrome source data in either the 8-bpp mode or the 16-bpp mode.
GP_PAT_COLOR_0 and GP_PAT_COLOR_1
Graphics Pipeline Pattern Color Registers 0 and 1: These two registers determine
the colors used when expanding pattern data.
GP_PAT_COLOR_2 and GP_PAT_COLOR_3
Graphics Pipeline Pattern Color Registers 2 and 3:These two registers determine
the colors used when expanding pattern data.
GP_PAT_DATA 0 through 3
Graphics Pipeline Pattern Data Registers 0 through 3: Together these registers
contain 128 bits of pattern data.
GP_PAT_DATA_0 corresponds to bits [31:0] of the pattern data.
GP_PAT_DATA_1 corresponds to bits [63:32] of the pattern data.
GP_PAT_DATA_2 corresponds to bits [95:64] of the pattern data.
GP_PAT_DATA_3 corresponds to bits [127:96] of the pattern data.
GP_VGA_WRITE
Graphics Pipeline VGA Write Patch Control Register: Controls the VGA memory
write path in the graphics pipeline.
GP_VGA_READ
Graphics Pipeline VGA Read Patch Control Register: Controls the VGA memory
read path in the graphics pipeline.
GP_RASTER_MODE
Graphics Pipeline Raster Mode Register: This register controls the manipulation
of the pixel data through the graphics pipeline. Refer to Section 4.4.5 “Raster
Operations” on page 128.
GP_VECTOR_MODE
Graphics Pipeline Vector Mode Register: Writing to this register initiates the ren-
dering of a vector.
GP_BLT_MODE
Graphics Pipeline BLT Mode Register: Writing to this initiates a BLT operation.
Default Value
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxxxxxh
00000000h
00000000h
00000000h
00000000h
Revision 1.0
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