GX1 Datasheet, PDF (182/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Power Management (Continued)
5.3 POWER MANAGEMENT REGISTERS
The GX1 processor contains the power management reg-
isters for the serial packet transmission control, the user-
defined power management address space, Suspend
Refresh, and SMI status for Suspend/Resume. These
registers are memory mapped (GX_BASE+8500h-8FFFh)
in the address space of the GX1 processor and are
described in the following sections. Refer to Section 4.1.2
“Control Registers” on page 99 for instructions on access-
ing these registers.
Note, however, the PM_BASE and PM_MASK registers
are accessed with the CPU_READ and CPU_WRITE
instructions. Refer to Section 4.1.6 “CPU_READ/
CPU_WRITE Instructions” on page 102 for more informa-
tion regarding these instructions.
Table 5-1 summarizes the above mentioned registers.
Tables 5-2 and 5-3 give these register’s bit formats.
Table 5-1. Power Management Register Summary
GX_BASE+
Memory Offset
Type Name/Function
Control and Status Registers
8500h-8503h
8504h-8507h
8508h-850Bh
850Ch-850Fh
R/W
PM_STAT_SMI
PM SMI Status register: Contains System Management Mode (SMM) status infor-
mation used by SoftVGA.
R/W
PM_CNTRL_TEN
PM Serial Packet Control register: Sets the serial packet transmission frequency
and enables specific CPU events to be recorded in the serial packet.
R/W
PM_CNTRL_CSTP
PM Clock Stop Control register: Enables the 3V Suspend Mode for the GX1 pro-
cessor.
R/W
PM_SER_PACK
PM Serial Packet register: Transmits the contents of the serial packet.
Programmable Address Region Registers
FFFFFF6Ch
FFFFFF7Ch
R/W
PM_BASE
PM Base register: Contains the base address for the programmable memory
range decode. This register, in combination with the PM_MASK register, is used to
generate a memory range decode which sets bit 1 in the serial transmission
packet.
R/W
PM_MASK
PM Mask register: The address mask for the PM_BASE register
Default
Value
xxxxxx00h
xxxxxx00h
xxxxxx00h
xxxxxx00h
00000000h
00000000h
Table 5-2. Power Management Control and Status Registers
Bit
Name
Description
GX_BASE+8500h-8503h
PM_STAT_SMI Register (R/W)
Default Value = xxxxxx00h
31:8
RSVD
Reserved: These bits are not used. Do not write to these bits.
7:3
RSVD
Reserved: Set to 0.
2
SMI_MEM
SMI VGA Emulation Memory: This bit is set high if a SMI was generated for VGA emulation in
response to a VGA memory access. An SMI can be generated on a memory access to one of three
regions in the A0000h to BFFFFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on
page 104)
1
SMI_IO
SMI VGA Emulation I/O: This bit is set high if a SMI was generated for VGA emulation in response
to an I/O access. An SMI can be generated on a I/O access to one of three regions in the 3B0h to
3DFh range as specified in the BC_XMAP_1 register. (See Table 4-9 on page 104)
0
SMI_PIN
SMI Pin: When set high, this bit indicates that the SMI# input pin has been asserted to the
GX1 processor.
Note: These bits are “sticky” bits and can only be cleared with a write of ‘1’ to the respective bit.
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