GX1 Datasheet, PDF (85/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.7.2 SMI# Pin
External chipsets can generate an SMI based on numer-
ous asynchronous events, including power management
timers, I/O address trapping, external devices, audio FIFO
events, and others. Since SMI# is edge sensitive, the
chipset must generate an edge for each of the events
above, requiring arbitration and storage of multiple SMM
events. These functions are provided by the CS5530 I/O
companion device. The processor generates an SMI when
the external pin changes from high-to-low or when an
Resume (RSM) occurs if SMI# has not remained low since
the initiation of the previous SMI.
3.7.3 SMM Configuration Registers
The SMAR register specifies the base location of SMM
code region and its size limit.
The SMHR register specifies the 32-bit physical address of
the SMM header. The SMHR address must be 32-bit
aligned as the bottom two bits are ignored by the micro-
code. Hardware will detect write operations to SMAR, and
signal the microcode to recompute the header address.
Access to the SMAR and SMHR registers is enabled by
MAPEN (Index C3h[4] see bit details on page 52).
The SMAR register writes to the SMHR register when the
SMAR register is changed. For this reason, changes to the
SMAR register should be completed prior to setting up the
SMHR register. The configuration registers bit formats are
detailed in Table 3-11 beginning on page 52.
3.7.4 SMM Memory Space Header
Tables 3-34 and 3-35 show the SMM header. A memory
address field has been added to the end (offset –40h) of
the header for the GX1 processor. Memory data will be
stored overlapping the I/O data, since these events cannot
occur simultaneously. The I/O address is valid for both IN
and OUT instructions, and I/O data is valid only for OUT.
The memory address is valid for read and write operations,
and memory data is valid only for write operations.
With every SMI interrupt or SMINT instruction, selected
CPU state information is automatically saved in the SMM
memory space header located at the top of SMM address
space. The header contains CPU state information that is
modified when servicing an SMM interrupt. Included in this
information are two pointers. The Current IP points to the
instruction executing when the SMI was detected, but it is
valid only for an internal I/O SMI.
The Next IP points to the instruction that will be executed
after exiting SMM. The contents of Debug Register 7
(DR7), the Extended Flags register (EFLAGS), and Control
Register 0 (CR0) are also saved. If SMM has been entered
due to an I/O trap for a REP INSx or REP OUTSx instruc-
tion, the Current IP and Next IP fields contain the same
addresses. In addition, the I and P fields contain valid infor-
mation.
If entry into SMM is the result of an I/O trap, it is useful for
the programmer to know the port address, data size and
data value associated with that I/O operation. This informa-
tion is also saved in the header and is valid only if SMI# is
asserted during an I/O bus cycle. The I/O trap information is
not restored within the CPU when executing a RSM instruction.
Table 3-34. SMM Memory Space Header
Mem.
Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–04h
–08h
–0Ch
DR7
EFLAGS
CR0
–10h
–14h
–18h
–1Ch
–20h
–24h
–28h
–2Ch
–30h
–34h
RSVD
RSVD
I/O Data Size
Current IP
Next IP
CS Descriptor [63:32]
CS Descriptor [31:0]
RSVD
I/O or Memory Data [31:0]¹
Restored ESI or EDI
I/O or Memory Address [31:0]
CS Selector
NV XMHS P I C
I/O Address [15:0]
1. Check the M bit at Offset 24h to determine if the data is memory or I/O.
Revision 1.0
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