GX1 Datasheet, PDF (97/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.1 INTEGRATED FUNCTIONS PROGRAMMING INTERFACE
The GX1 processor’s integrated functions programming Figure 4-2 on page 98 shows the complete memory
interface is a memory mapped space. The control registers address map for the GX1 processor. When accessing the
for the graphics pipeline, display controller, and memory GX1 processor memory space, address bits [29:24] must
controller are located in this space, as well as all the graph- be zero. This means that the GX1 processor accesses a
ics memory: frame buffer, compression buffer, etc. This linear address space with a total of 16 MB. Address bit 23
memory address space is referred to as the GX1 processor divides this space into 8 MB for control (bit 23 = 0) and 8
memory space.
MB for graphics memory (bit 23 = 1). In control space, bits
4.1.1 Graphics Control Register
The base address for these memory mapped registers is
[22:16] are not decoded, so the programmer should set
them to zero. Address bit 15 divides the remaining 64 KB
address space into scratchpad RAM and PCI access (bit
programmed in the Graphics Configuration Register (GCR,
Index B8h, bits[1:0]), shown in Table 4-1. The GCR only
specifies address bits [31:30] of physical memory. The
remaining address bits [29:0] are fixed to zero. The GCR is
I/O mapped because it must be accessed before memory
mapping can be enabled. Refer to Section 3.3.2.2 “Config-
uration Registers” on page 50 for information on how to
access this register.
The GX1 processor incorporates graphics functions that
require registers to implement and control them. Most of
these registers are memory mapped and physically located
in the logical units they control. The mapping of these units
is controlled by the GCR register.
15 = 0) and control registers (bit 15 = 1). Note that scratch-
pad RAM is placed here by programming the tags appropri-
ately.
Device drivers are responsible for performing physical-to-
virtual memory-address translation, including allocation of
selectors that point to the GX1 processor. All memory
decoded by the processor may be accessed in protected
mode by creating a selector with the physical address
equal to the GX1 Base Address, shown in Table 4-1, and a
limit of 16 MB. Additionally, a selector with only a 64 KB
limit is large enough to access all of the GX1 processor’s
registers and scratchpad RAM.
Bit
Name
Index B8h
7:4
RSVD
3:2
SP
1:0
GX
Table 4-1. Graphics Control Register (GCR)
Description
GCR Register (R/W)
Default Value = 00h
Reserved: Set to 0.
Scratchpad Size: Specifies the size of the scratchpad cache.
00 = 0 KB; Graphics instruction disabled (see Section 4.1.5 “Display Driver Instructions” on page 102).
01 = 2 KB
10 = 3 KB
11 = 4 KB
GX1 Base Address: Specifies the physical address for the base (GX_BASE) of the scratchpad RAM, the
graphics memory (frame buffer, compression buffer, etc.) and the other memory mapped registers.
00 = Scratchpad RAM, Graphics Subsystem, and memory-mapped configuration registers are disabled.
01 = Scratchpad RAM and control registers start at GX_BASE = 40000000h.
10 = Scratchpad RAM and control registers start at GX_BASE = 80000000h.
11 = Scratchpad RAM and control registers start at GX_BASE = C0000000h.
Revision 1.0
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