GX1 Datasheet, PDF (101/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Table 4-4. L1 Cache BitBLT Register Summary
Mnemonic Name¹
Function²
L1_BB0_BASE
L1 Cache BitBLT 0 Base Address
Contains the L1 set 0 address to the first byte of BLT Buffer 0.
L1_BB0_POINTER
L1 Cache BitBLT 0 Pointer
L1_BB1_BASE
L1 Cache BitBLT 1 Base Address
L1_BB1_POINTER
L1 Cache BitBLT 1 Pointer
Contains the L1 set 0 address offset to the current line of BLT Buffer 0.
Contains the L1 set 0 address to the first byte of BLT Buffer 1.
Contains the L1 set 0 address offset to the current line of BLT Buffer 1.
1. For information on accessing these registers, refer to Section 4.1.6 “CPU_READ/CPU_WRITE Instructions” on page
102.
2. The L1 cache locations accessed by the BitBLT registers must be enabled as scratchpad RAM prior to use.
Bit
15:12
11:4
3:0
15:12
11:4
3:0
15:12
11:4
3:0
15:12
11:4
3:0
Name
RSVD
INDEX
BYTE
RSVD
INDEX
RSVD
RSVD
INDEX
BYTE
RSVD
INDEX
RSVD
Table 4-5. L1 Cache BitBLT Registers
Description
L1_BB0_BASE Register (R/W)
Default Value = None
Reserved: Set to 0.
BitBLT 0 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 0.
BitBLT 0 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 0.
L1_BB0_POINTER Register (R/W)
Default Value = None
Reserved: Set to 0.
BitBLT 0 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 0.
Reserved: Set to 0.
L1_BB1_Base Register (R/W)
Default Value = None
Reserved: Set to 0.
BitBLT 1 Base Index: The index to the starting cache line of set 0 in L1 of BLT Buffer 1.
BitBLT 1 Starting Byte: Determines which byte of the starting line is the beginning of BLT Buffer 1.
L1_BB1_POINTER Register (R/W)
Default Value = None
Reserved: Set to 0.
BitBLT 1 Pointer Index: The index to the current cache line of set 0 in L1 of BLT Buffer 1.
Reserved: Set to 0.
Revision 1.0
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