GX1 Datasheet, PDF (157/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5.14.1 CS5530 Video Port Data Transfer
VID_VAL indicates that the GX1 processor has placed valid
data on VID_DATA[7:0]. VID_RDY indicates that the
CS5530 is ready to accept the next byte of video data.
VID_DATA[7:0] is advanced when both VID_VAL and
VID_RDY are asserted. VID_RDY is driven one clock early
to the GX1 processor while VID_VAL is driven coincident
with VID_DATA[7:0]. A sample interface functional timing
diagram is shown in Figure 4-17.
VID_CLK
VID_VAL
8 CLKs
8 + 3 CLKs
VID_RDY
VID_DATA [7:0]
Invalid Data
8 CLKs
Note: VID_CLK = CORE_CLK/2
3 CLKs
4 CLKs
1
2
1
2
CLK CLKs CLK CLKs
2
CLKs
Figure 4-17. Video Port Data Transfer (CS5530)
4 CLKs
Revision 1.0
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