GX1 Datasheet, PDF (57/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.3.2.4 TLB Test Registers
Two test registers are used in testing the processor’s Trans-
lation Lookaside Buffer (TLB), TR6 and TR7. Table 3-14 is a
register map for the TLB Test Registers with their bit defini-
tions given in Table 3-15 on page 58. The test registers are
accessed through MOV instructions that can be executed
only at privilege level 0 (real mode is always privilege level
0).
The processor’s TLB is a 32-entry, four-way set associative
memory. Each TLB entry consists of a 24-bit tag and 20-bit
data. The 24-bit tag represents the high-order 20 bits of the
linear address, a valid bit, and three attribute bits. The 20-
bit data portion represents the upper 20 bits of the physical
address that corresponds to the linear address.
The TLB Test Control Register (TR6) contains a command
bit, the upper 20 bits of a linear address, a valid bit and the
attribute bits used in the test operation. The contents of
TR6 are used to create the 24-bit TLB tag during both write
and read (TLB lookup) test operations. The command bit
defines whether the test operation is a read or a write.
The TLB Test Data Register (TR7) contains the upper 20
bits of the physical address (TLB data field), three LRU
bits, two replacement (REP) bits, and a control bit (PL).
During TLB write operations, the physical address in TR7 is
written into the TLB entry selected by the contents of TR6.
During TLB lookup operations, the TLB data selected by
the contents of TR6 is loaded into TR7. Table 3-15 lists the
bit definitions for TR7 and TR6.
Table 3-14. TLB Test Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TR7 Register
TR6 Register
TLB Test Data Register (R/W)
Physical Address
0 0 TLB LRU 0 0 P REP 0 0
L
TLB Test Control Register (R/W)
Linear Address
VDDUURR0 0 0 0C
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