GX1 Datasheet, PDF (199/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Electrical Specifications (Continued)
Table 6-14. Clock Signals (Refer to Figures 6-5 and 6-6) (Continued)
SYSCLK = 33 MHz
Symbol
Parameter
Min
Typ
Max
Units
t13
SDCLK_OUT, SDCLK[3:0] Rise Time²
200 MHz / 3
0.45
ns
233 MHz / 3
0.45
233 MHz / 3.5
0.45
266 MHz / 3.5
0.45
266 MHz / 4
0.45
300 MHz / 4
0.45
1. A SYSCLK of 30 MHz corresponds to a core frequency of 180 MHz. A SYSCLK of 33 MHz corresponds to core frequen-
cies of 166, 200, 233, and 266 MHz.
2. SDCLK_OUT and SYSCLK rise and fall times are measured between V_IH min and V_IL max with a 50 pF load.
3. SDCLK calculations are based on the following configurations:
200 MHz (6x) / 3 = 66.7 MHz SDCLK_OUT
233 MHz (7x) / 3 = 77.7 MHz SDCLK_OUT
266 MHz (8x) / 3.5 = 76 MHz SDCLK_OUT
300 MHz (9x) / 4 = 75 MHz SDCLK_OUT
Revision 1.0
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