GX1 Datasheet, PDF (42/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
Table 3-1. Initialized Core Register Controls (Continued)
Register
Register Name
Initialized Contents¹
Comments
CCR1
CCR2
CCR3
CCR4
CCR7
SMHR
SMAR
DIR0
Configuration Control 1
Configuration Control 2
Configuration Control 3
Configuration Control 4
Configuration Control 7
SMM Header Address
SMM Address 0
Device Identification 0
DIR1
Device Identification 1
DR7
Debug Register 7
1. x = Undefined value
00h
00h
00h
00h
00h
000000h
000000h
4xh
xxh
00000400h
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 52 for bit definitions.
See Table 3-11 on page 53 for bit definitions.
See Table 3-11 on page 53 for bit definitions.
See Table 3-11 on page 54 for bit definitions
See Table 3-11 on page 54 for bit definitions.
Device ID and reads back initial CPU clock-speed set-
ting. See Table 3-11 on page 54 for bit definitions.
Stepping and Revision ID (RO). See Table 3-11 on
page 54 for bit definitions.
See Table 3-13 on page 56 for bit definitions.
3.2 INSTRUCTION SET OVERVIEW
The GX1 processor instruction set can be divided into nine
types of operations:
• Arithmetic
• Bit Manipulation
• Shift/Rotate
• String Manipulation
• Control Transfer
• Data Transfer
• Floating Point
• High-Level Language Support
• Operating System Support
The GX1 processor instructions operate on as few as zero
operands and as many as three operands. A NOP (no
operation) instruction is an example of a zero-operand
instruction. Two-operand instructions allow the specifica-
tion of an explicit source and destination pair as part of the
instruction. These two-operand instructions can be divided
into ten groups according to operand types:
• Register to Register
• Register to Memory
• Memory to Register
• Memory to Memory
• Register to I/O
• I/O to Register
• Memory to I/O
• I/O to Memory
• Immediate Data to Register
• Immediate Data to Memory
An operand can be held in the instruction itself (as in the
case of an immediate operand), in one of the processor’s
registers or I/O ports, or in memory. An immediate operand
is fetched as part of the opcode for the instruction.
Operand lengths of 8, 16, 32 or 48 bits are supported as
well as 64 or 80 bits associated with floating-point instruc-
tions. Operand lengths of 8 or 32 bits are generally used
when executing code written for 386- or 486-class (32-bit
code) processors. Operand lengths of 8 or 16 bits are gen-
erally used when executing existing 8086 or 80286 code
(16-bit code). The default length of an operand can be
overridden by placing one or more instruction prefixes in
front of the opcode. For example, the use of prefixes allows
a 32-bit operand to be used with 16-bit code or a 16-bit
operand to be used with 32-bit code.
Section 8.3 “Processor Core Instruction Set” on page 222
contains the clock count table that lists each instruction in
the CPU instruction set. Included in the table are the asso-
ciated opcodes, execution clock counts, and effects on the
EFLAGS register.
3.2.1 Lock Prefix
The LOCK prefix may be placed before certain instructions
that read, modify, then write back to memory. The PCI will
not be granted access in the middle of locked instructions.
The LOCK prefix can be used with the following instructions
only when the result is a write operation to memory.
• Bit Test Instructions (BTS, BTR, BTC)
• Exchange Instructions (XADD, XCHG, CMPXCHG)
• One-Operand Arithmetic and Logical Instructions (DEC,
INC, NEG, NOT)
• Two-Operand Arithmetic and Logical Instructions (ADC,
ADD, AND, OR, SBB, SUB, XOR).
An invalid opcode exception is generated if the LOCK pre-
fix is used with any other instruction or with one of the
instructions above when no write operation to memory
occurs (for example, when the destination is a register).
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