GX1 Datasheet, PDF (47/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.3.2 System Register Set
The System Register Set, shown in Table 3-5, consists of
registers not generally used by application programmers.
These registers are typically employed by system level pro-
grammers who generate operating systems and memory
management programs. Associated with the System Reg-
ister Set are certain tables and segments which are listed
in Table 3-5.
The Control Registers control certain aspects of the GX1
processor such as paging, coprocessor functions, and seg-
ment protection.
The Configuration Registers are used to define the GX1
CPU setup including cache management.
The Debug Registers provide debugging facilities for the
GX1 processor and enable the use of data access break-
points and code execution breakpoints.
The Test Registers provide a mechanism to test the con-
tents of both the on-chip 16 KB cache and the Translation
Lookaside Buffer (TLB).
The Descriptor Table Register hold descriptors that man-
age memory segments and tables, interrupts and task
switching. The tables are defined by corresponding regis-
ters.
The two Task State Segment Tables defined by TSS reg-
ister are used to save and load the computer state when
switching tasks.
The ID Registers allow BIOS and other software to identify
the specific CPU and stepping.
System Management Mode (SMM) control information is
stored in the SMM Registers.
Table 3-5 lists the system register sets along with their size
and function.
Table 3-5. System Register Set
Group
Name
Function
Width
(Bits)
Control
CR0
System Control
32
Registers
Register
CR2
Page Fault Linear
32
Address Register
CR3
Page Directory Base
32
Register
CR4
Time Stamp Counter
32
Configuration CCRn
Configuration Con-
8
Registers
trol Registers
Debug
DR0
Linear Breakpoint
32
Registers
Address 0
DR1
Linear Breakpoint
32
Address 1
DR2
Linear Breakpoint
32
Address 2
DR3
Linear Breakpoint
32
Address 3
DR6
Breakpoint Status
32
DR7
Breakpoint Control
32
Test
TR3
Cache Test
32
Registers
TR4
Cache Test
32
TR5
Cache Test
32
TR6
TLB Test Control
32
TR7
TLB Test Data
32
Descriptor
GDT
General Descriptor
32
Tables
Table
IDT
Interrupt Descriptor
32
Table
LDT
Local Descriptor
16
Table
Descriptor
GDTR
GDT Register
32
Table
Registers
IDTR
IDT Register
32
LDTR
LDT Register
16
Task State
TSS
Segment and
Registers
TR
Task State Segment
16
Table
TSS Register Setup
16
ID
Registers
DIRn
Device Identification
8
Registers
SMM
SMARn SMM Address
8
Registers
Region Registers
SMHRn SMM Header
8
Addresses
Performance PCR0
Performance Con-
8
Registers
trol Register
Revision 1.0
47
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