GX1 Datasheet, PDF (135/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
4.5.1 Display FIFO
The display controller contains a large (64x64 bit) FIFO for
queuing up display data from the memory controller as
required for output to the screen. The memory controller
must arbitrate between display controller requests and
other requests for memory access from the microprocessor
core, L1 cache controller, and the graphics pipeline.
Display data is required in real time, making it the highest
priority in the system. Without efficient memory manage-
ment, system performance would suffer dramatically due to
the constant display-refresh requests from the display con-
troller. The large size of the display FIFO is desirable so
that the FIFO may primarily be loaded during times when
there is no other request pending to the DRAM controller
which allows the memory controller to stay in page mode
for a longer period of time when servicing the display FIFO.
When a priority request from the cache or graphics pipeline
occurs, if the display FIFO has enough data queued up, the
DRAM controller can immediately service the request with-
out concern that the display FIFO will underflow. If the dis-
play FIFO is below a programmable threshold, a high-
priority request will be sent to the DRAM controller, which
will take precedence over any other requests that are pend-
ing.
The display FIFO is 64 bits wide to accommodate high-
speed burst read operations from the DRAM controller at
maximum memory bandwidth. In addition to the normal
pixel data stream, the display FIFO also queues up cursor
patterns.
4.5.2 Compression Technology
To reduce the system memory contention caused by the
display refresh, the display controller contains compression
and decompression logic for compressing the frame buffer
image in real time as it is sent to the display. It combines
this compressed display buffer into the extra off-screen
memory within the graphics memory aperture. Coherency
of the compressed display buffer is maintained by use of
dirty and valid bits for each line. The dirty and valid RAM is
contained on-chip for maximum efficiency. Whenever a line
has been validly compressed, it will be retrieved from the
compressed display buffer for all future accesses until the
line becomes dirty again. Dirty lines will be retrieved from
the normal uncompressed frame buffer.
The compression logic has the ability to insert a program-
mable number of "static" frames, during which time dirty
bits are ignored and the valid bits are read to determine
whether a line should be retrieved from the frame buffer or
compressed display buffer. The less frequently the dirty bits
are sampled, the more frequently lines will be retrieved
from the compressed display buffer. This allows a program-
mable screen image update rate (as opposed to refresh
rate). Generally, an update rate of 30 frames per second is
adequate for displaying most types of data, including real-
time video. If a flat panel display is used that has a slow
response time, such as 100 ms, the image need not be
updated faster than ten frames per second, since the panel
could not display changes beyond that rate.
The compression algorithm used in the GX1 processor
commonly achieves compression ratios between 10:1 and
20:1, depending on the nature of the display data. This
high level of compression provides higher system perfor-
mance by reducing typical latency for normal system mem-
ory access, higher graphics performance by increasing
available drawing bandwidth to the DRAM array, and much
lower power consumption by significantly reducing the
number of off-chip DRAM accesses required for refreshing
the display. These advantages become even more pro-
nounced as display resolution, color depth, and refresh rate
are increased and as the size of the installed DRAM
increases.
As uncompressed lines are fed to the display, they will be
compressed and stored in an on-chip compressed line
buffer (64x32 bits). Lines will not be written back to the
compressed display buffer in the DRAM unless a valid
compression has resulted, so there is no penalty for patho-
logical frame buffer images where the compression algo-
rithm breaks down.
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