GX1 Datasheet, PDF (68/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
Real and Virtual 8086 Modes
Logical Address
Segment Selector
15
INDEX
0
INSTRUCTION OFFSET
Logical
Address
x 16
+
Base
Address
p = Paging mechanism for virtual 8086 mode only
Linear
Address
p
Physical
Address
Segment
Main Memory
Protected Mode
Logical Address
Segment Selector
15
3 21 0
INDEX
TI RPL INSTRUCTION OFFSET
÷8
Segment Descriptor
Base
+
p
Linear
Physical
Address
Address
Address
GDT or LDT Descriptor Table
p = Paging mechanism
Segment
Main Memory
Figure 3-6. Selector Mechanisms
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