GX1 Datasheet, PDF (217/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.1.5.2 index Field (Index Selection)
The index field (Table 8-14) specifies the index register
used by the offset mechanism for offset address calcula-
tion. When no index register is used (index field = 100), the
ss value must be 00 or the effective address is undefined.
Table 8-14. index Field Encoding
Index Field
Index Register
000
EAX
001
ECX
010
EDX
011
EBX
100
none
101
EBP
110
ESI
111
EDI
8.1.5.3 Base Field (s-i-b Present)
In Table 8-8, the note “s-i-b is present” for certain entries
forces the use of the mod and base field as listed in Table
8-15. The first two digits in the first column of Table 8-15
identifies the mod bits in the mod r/m byte. The last three
digits in the first column of this table identify the base fields
in the s-i-b byte.
Table 8-15. mod base Field Encoding
mod Field
within
mode/rm
Byte
(bits 7:6)
base Field
within
s-i-b
Byte
(bits 2:0)
32-Bit Address Mode
with mod r/m and s-i-b
Bytes Present
00
000
DS:[EAX+(scaled index)]
00
001
DS:[ECX+(scaled index)]
00
010
DS:[EDX+(scaled index)]
00
011
DS:[EBX+(scaled index)]
00
100
SS:[ESP+(scaled index)]
00
101
DS:[d32+(scaled index)]
00
110
DS:[ESI+(scaled index)]
00
111
DS:[EDI+(scaled index)]
01
000
DS:[EAX+(scaled index)+d8]
01
001
DS:[ECX+(scaled index)+d8]
01
010
DS:[EDX+(scaled index)+d8]
01
011
DS:[EBX+(scaled index)+d8]
01
100
SS:[ESP+(scaled index)+d8]
01
101
SS:[EBP+(scaled index)+d8]
01
110
DS:[ESI+(scaled index)+d8]
01
111
DS:[EDI+(scaled index)+d8]
10
000
DS:[EAX+(scaled index)+d32]
10
001
DS:[ECX+(scaled index)+d32]
10
010
DS:[EDX+(scaled index)+d32]
10
011
DS:[EBX+(scaled index)+d32]
10
100
SS:[ESP+(scaled index)+d32]
10
101
SS:[EBP+(scaled index)+d32]
10
110
DS:[ESI+(scaled index)+d32]
10
111
DS:[EDI+(scaled index)+d32]
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