GX1 Datasheet, PDF (53/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
Table 3-11. Configuration Registers (Continued)
Bit
Name
Description
0
Note:
SMI_LOCK
SMM Register Lock:
If = 1: SMM Address Region Register (SMAR[31:0]), SMAC (CCR1[2]), USE_SMI (CCR1[1])
cannot be modified unless in SMM routine. Once set, SMI_LOCK can only be cleared by asserting
the RESET pin.
All bits are cleared to zero at reset.
Index E8h
CCR4 — Configuration Control Register 4 (R/W)
Default Value = 85h
7
CPUID
Enable CPUID Instruction:
If = 1: The ID bit in the EFLAGS register to be modified and execution of the CPUID instruction occurs
as documented in Section 8.2 “CPUID Instruction” on page 218.
If = 0: The ID bit can not be modified and execution of the CPUID instruction causes an invalid opcode
exception.
6
SMI_NEST
SMI Nest:
If = 1: SMI interrupts can occur during SMM mode. SMM service routines can optionally set
SMI_NEST high to allow higher-priority SMI interrupts while handling the current event
5
FPU_FAST_EN FPU Fast Mode Enable:
If 0 = Disable FPU Fast Mode.
If 1 = Enable FPU Fast Mode
4
DTE_EN
Directory Table Entry Cache:
If = 1: Enables directory table entry to be cached.
Cleared to 0 at reset.
3
MEM_BYP
Memory Read Bypassing:
If = 1: Enables memory read bypassing.
Cleared to 0 at reset.
2:0
IORT(2:0)
I/O Recovery Time: Specifies the minimum number of bus clocks between I/O accesses:
000 = No clock delay
001 = 2-clock delay
010 = 4-clock delay
011 = 8-clock delay
100 = 16-clock delay
101 = 32-clock delay (default value after reset)
110 = 64-clock delay
111 = 128-clock delay
Note: MAPEN (CCR3[4]) must = 1 to read or write this register.
Index EBh
CCR7 — Configuration Control Register 7 (R/W)
Default Value = 00h
7:3
RSVD
Reserved: Set to 0.
2
NMI
Generate NMI:
If = 0 Do nothing
If = 1 Generate NMI
In order to generate multiple NMIs, this bit must be set to zero between each setting of 1.
1
RSVD
Reserved: Set to 0.
0
EMMX
Extended MMX Instructions Enable:
If = 1: Extended MMX instructions are enabled
Index 20h
PCR — Performance Control Register (R/W)
Default Value = 07h
7
LSSER
Load/Store Serialize Enable (Reorder Disable): LSSER should be set to ensure that memory
mapped I/O devices operating outside of the address range 640 KB to 1 MB will operate correctly. For
memory accesses above 1 GByte, refer to CCR3[7:5] (LSS_34, LSS_23, LSS_12.)
If = 1: All memory read and write operations will occur in execution order (load/store serializing
enabled, reordering disabled).
If = 0: Memory reads and write can be reordered for optimum performance (load/store serializing dis-
abled, reordering enabled).
Memory accesses in the address range 640 KB to 1 MB will always be issued in execution order.
6
RSVD
Reserved: Set to 0.
5
RSVD
Reserved: Set to 1.
4:0
RSVD
Reserved: Set to 0.
Note: MAPEN (CCR3[4]) must = 1 to read or write this register.
Revision 1.0
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