GX1 Datasheet, PDF (133/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Table 4-24. Graphics Pipeline Configuration Registers (Continued)
Bit
Name
Description
1:0
Note:
RS
Source Data: Specifies the source data location.
00 = No source data is required. The source data into the raster operation unit is all ones.
01 = Read source data from the frame buffer (temporarily stored in BLT Buffer 0).
10 = Read source data from BLT Buffer 0.
11 = Read source data from BLT Buffer 1.
Writing to this register launches a BLT operation.
GX_BASE+820Ch-820Fh
GP_BLT_STATUS Register (R/W)
Default Value = 00000000h
31:10
9
8
7:3
2
1
0
RSVD
W
M
RSVD
BP (RO)
PB (RO)
BB (RO)
Reserved: Set to 0.
Screen Width: Selects a frame-buffer width of 2048 bytes (default is 1024 bytes). This register must be
programmed correctly in order for compression to work.
16-bpp Mode: Selects a pixel data format of 16-bpp (default is 8-bpp).
Reserved: Set to 0.
BLT Pending (Read Only): Indicates that a BLT operation is pending in the master registers.
The “BLT Pending” bit must be clear before loading any of the graphics pipeline registers. Loading registers
when this bit is set high will destroy the values for the pending BLT.
Pipeline Busy (Read Only): Indicates that the graphics pipeline is processing data.
The “Pipeline Busy” bit differs from the “BLT Busy” bit in that the former only indicates that the graphics
pipeline is processing data. The “BLT Busy” bit also indicates that the memory controller has not yet pro-
cessed all of the requests for the current operation.
The “Pipeline Busy” bit must be clear before loading a BLT buffer if the previous BLT operation used the
same BLT buffer.
BLT Busy (Read Only): Indicates that a BLT / vector operation is in progress.
The “BLT Busy” bit must be clear before accessing the frame buffer directly.
GX_BASE+8210h-8213h
GP_VGA_BASE (R/W)
Default Value = xxxxxxxxh
Note that the registers at GX_BASE+8210h is located in the area designated for the graphics pipeline but is used for VGA emulation
purposes. Refer to Table 4-39 on page 166 for this register’s bit formats.
GX_BASE+8214h-8217h
GP_VGA_LATCH Register (R/W)
Default Value = xxxxxxxxh
Note that the registers at GX_BASE+8214h is located in the area designated for the graphics pipeline but is used for VGA emulation
purposes. Refer to Table 4-39 on page 166 for this register’s bit formats.
Revision 1.0
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