GX1 Datasheet, PDF (222/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.3 PROCESSOR CORE INSTRUCTION SET
The instruction set for the GX1 processor core is summa-
rized in Table 8-27. The table uses several symbols and
abbreviations that are described next and listed in Table 8-
26.
8.3.1 Opcodes
Opcodes are given as hex values except when they appear
within brackets as binary values.
8.3.2 Clock Counts
The clock counts listed in the instruction set summary table
are grouped by operating mode (real and protected) and
whether there is a register/cache hit or a cache miss. In
some cases, more than one clock count is shown in a col-
umn for a given instruction, or a variable is used in the
clock count.
8.3.3 Flags
There are nine flags that are affected by the execution of
instructions. The flag names have been abbreviated and various
conventions used to indicate what effect the instruction has
on the particular flag.
Table 8-26. Processor Core Instruction Set
Table Legend
Symbol or
Abbreviatio
n
Description
Opcode
#
##
###
+
+++
Clock Count
/
n
L
|
\
Flags
OF
DF
IF
TF
SF
ZF
AF
PF
CF
x
-
0
1
u
Immediate 8-bit data.
Immediate 16-bit data.
Full immediate 32-bit data (8, 16, 32 bits).
8-bit signed displacement.
Full signed displacement (16, 32 bits).
Register operand/memory operand.
Number of times operation is repeated.
Level of the stack frame.
Conditional jump taken | Conditional jump not
taken. (e.g. “4|1” = 4 clocks if jump taken, 1
clock if jump not taken).
CPL ≤ IOPL \ CPL > IOPL
(where CPL = Current Privilege Level, IOPL =
I/O Privilege Level).
Overflow Flag.
Direction Flag.
Interrupt Enable Flag.
Trap Flag.
Sign Flag.
Zero Flag.
Auxiliary Flag.
Parity Flag.
Carry Flag.
Flag is modified by the instruction.
Flag is not changed by the instruction.
Flag is reset to “0”.
Flag is set to “1”.
Flag is undefined following execution the
instruction.
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