GX1 Datasheet, PDF (181/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Power Management (Continued)
5.2.3 Stopping the Input Clock
The GX1 processor is a static device, allowing the input
clock (SYSCLK) to be stopped and restarted without any
loss of internal CPU data. The SYSCLK input can be
stopped at either a logic high or logic low state. The
required sequence for stopping SYSCLK is to initiate 3 Volt
Suspend, wait for the assertion of SUSPA# by the proces-
sor, and then stop the input clock.
The CPU remains suspended until SYSCLK is restarted
and the Suspend mode is exited as described earlier.
While SYSCLK is stopped, the processor can no longer
sample and respond to any input stimulus including
REQx#, NMI, SMI#, INTR, and RESET inputs.
Figure 5-4 illustrates the recommended sequence for stop-
ping the SYSCLK using SUSP# to initiate 3 Volt Suspend.
SYSCLK may be started prior to or following negation of
the SUSP# input. The figure includes the SUSP_3V pin
from the Geode I/O companion which is used to stop the
external clocks.
5.2.4 Serial Packet Transmission
The GX1 processor transmits the contents of the “PM
Serial Packet" register on the SERIALP output pin to the
PSERIAL input pin of the Geode I/O companion. The GX1
processor holds SERIALP low until the transmission inter-
val counter (GX_BASE+8504h[4:3]) has elapsed. Once the
counter has elapsed, PSERIAL is held high for two
SYSCLKs to indicate the start of packet transmission.
The contents of the packet register are then shifted out
starting from bit 7 down to bit 0. PSERIAL is held high for
one SYSCLK to indicate the end of packet transmission
and then remains low until the next transmission interval.
After the packet transmission has completed, the packet
contents are cleared.
SYSCLK
SUSP#
SUSPA#
SUSP_3V
(I/O companion)
SMI Event, Timer or Pin
Figure 5-4. Stopping SYSCLK During Suspend Mode
Revision 1.0
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