GX1 Datasheet, PDF (82/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.6.5 Exceptions in Real Mode
Many of the exceptions described in Table 3-29 "Interrupt
Vector Assignments" on page 80 are not applicable in real
mode. Exceptions 10, 11, and 14 do not occur in real
mode. Other exceptions have slightly different meanings in
real mode as listed in Table 3-31.
Table 3-31. Exception Changes in Real Mode
Vector
Number
Protected Mode
Function
Real Mode
Function
8
Double fault.
Interrupt table limit overrun.
10
Invalid TSS.
Does not occur.
11
Segment not
present.
Does not occur.
12
Stack fault.
SS segment limit overrun.
13
General protec-
CS, DS, ES, FS, GS seg-
tion fault.
ment limit overrun. In pro-
tected mode, an error code
is pushed. In real mode, no
error code is pushed.
14
Page fault.
Does not occur.
3.6.6 Error Codes
When operating in protected mode, the following exceptions
generate a 16-bit error code:
• Double Fault
• Alignment Check
• Invalid TSS
• Segment Not Present
• Stack Fault
• General Protection Fault
• Page Fault
The error code format and bit definitions are shown in Table
3-32. Bits [15:3] (selector index) are not meaningful if the
error code was generated as the result of a page fault. The
error code is always zero for double faults and alignment
check exceptions.
Table 3-32. Error Codes
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Selector Index
S2
S1
S0
Fault
Type
Page
Fault
Selector Index
(Bits 15:3)
Reserved.
IDT Fault Index of faulty IDT
selector.
Table 3-33. Error Code Bit Definitions
S2 (Bit 2)
Fault caused by:
0 = Not present page
1 = Page-level protection
violation
Reserved
S1 (Bit 1)
Fault occurred during:
0 = Read access
1 = Write access
1
Segment Index of faulty
TI bit of faulty selector
0
Fault
selector.
S0 (Bit 0)
Fault occurred during:
0 = Supervisor access
1 = User access.
If = 1: exception occurred while
trying to invoke exception or
hardware interrupt handler.
If=1:
exception occurred while trying
to invoke exception or hardware
interrupt handler.
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