GX1 Datasheet, PDF (239/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.5 MMX INSTRUCTION SET
The CPU is functionally divided into the FPU unit, and the
integer unit. The FPU has been extended to process both
MMX instructions and floating point instructions in parallel
with the integer unit.
For example, when the integer unit detects an MMX
instruction, the instruction passes to the FPU unit for exe-
cution. The integer unit continues to execute instructions
while the FPU unit executes the MMX instruction. If another
MMX instruction is encountered, the second MMX instruc-
tion is placed in the MMX queue. Up to four MMX instruc-
tions can be queued.
The MMX instruction set is summarized in Table 8-31. The
abbreviations used in the table are listed Table 8-30.
Table 8-30. MMX Instruction Set Table Legend
Abbreviation
Description
<----
[11 mm reg]
mm
reg
<--sat--
<--move--
[byte]
[word]
[dword]
[qword]
[sign xxx]
mm1, mm2
mod r/m
pack
packdw
packwb
Result written.
Binary or binary groups of digits.
One of eight 64-bit MMX registers.
A general purpose register.
If required, the resultant data is saturated to
remain in the associated data range.
Source data is moved to result location.
Eight 8-bit BYTEs are processed in parallel.
Four 16-bit WORDs are processed in paral-
lel.
Two 32-bit DWORDs are processed in par-
allel.
One 64-bit QWORD is processed.
The BYTE, WORD, DWORD or QWORD
most significant bit is a sign bit.
MMX Register 1, MMX Register 2.
Mod and r/m byte encoding (Table 8-15 on
page 217).
Source data is truncated or saturated to
next smaller data size, then concatenated.
Pack two DWORDs from source and two
DWORDs from destination into four
WORDs in the destination register.
Pack four WORDs from source and four
WORDs from destination into eight BYTEs
in the destination register.
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