GX1 Datasheet, PDF (106/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Table 4-10. Region-Control-Field Bit Definitions
Bit
Position Function
3
PCI Accessible: The PCI slave can access this memory if this bit is set high and if the appropriate Read or Write Enable
bit is also set high.
2
Cache Enable¹: Caching this region of memory is inhibited if this bit is cleared.
1
Write Enable¹: Write operations to this region of memory are allowed if this bit is set high. If this bit is cleared, then write
operations in this region are directed to the PCI master.
0
Read Enable: Read operations to this region of memory are allowed if this bit is set high. If this bit is cleared then read
operations in this region are directed to the PCI master.
1. If Cache Enable = 1 and Write Enable = 1, the Write Enable determination occurs after the data has passed the cache. Since the cache
does write update, write data will change the cache if the address is cached. If a read then occurs to that address, the data will come
from the written data that is in the cache even though the address is not writable. If this must be avoided then do not make the region
cacheable.
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