GX1 Datasheet, PDF (180/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Power Management (Continued)
5.2.2 Initiating Suspend with SUSP#
The GX1 processor enters the Suspend mode in response
to SUSP# input assertion only when certain conditions are
met. First, the USE_SUSP bit must be set in CCR2 (Index
C2h[7]). In addition, execution of the current instructions
and any pending decoded instructions and associated bus
cycles must be completed. SUSP# is sampled on the rising
edge of SYSCLK, and must meet specified setup and hold
times to be recognized at a particular SYSCLK edge. See
Figure 5-2 for timing details.
When all conditions are met, the SUSPA# output is
asserted. The time from assertion of SUSP# to the activa-
tion of SUSPA# depends on which instructions were
decoded prior to assertion of SUSP#. Normally, once
SUSP# has been sampled inactive the SUSPA# output will
be deactivated within two clocks. However, the deactivation
of SUSPA# may be delayed until the end of an active
refresh cycle.
If the CPU is already in a Suspend mode initiated by
SUSP#, one occurrence of INTR and SMI# is stored for
execution after Suspend mode is exited. The CPU also
allows PCI master accesses during a SUSP#-initiated Sus-
pend mode. See Figure 5-3 for timing details. If an
unmasked REQx# is asserted, the GX1 processor will
deassert SUSPA# and exit Suspend mode to respond to
the PCI master access. If SUSP# is asserted when the PCI
master access is completed, REQx# deasserted, the GX1
processor will reassert SUSPA# and return to a SUSP#-ini-
tiated Suspend mode. If the CPU is in the middle of a PCI
master access when SUSP# is asserted, the assertion of
SUSPA# will be delayed until the PCI access is completed.
SYSCLK
SUSP#
SUSPA#
Figure 5-2. SUSP#-Initiated Suspend Mode
SYSCLK
REQx#
FRAME#
TRDY#
SUSP#
SUSPA#
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Figure 5-3. PCI Access During Suspend Mode
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