GX1 Datasheet, PDF (69/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
Selector Load Instruction
15
Selector
In Segment
Register
INDEX
0
TI RPL
Segment
Descriptor
Global Descriptor
Table
Segment Register
Selected By Decoded
Instruction
Segment
Caching
Cached Segment
and Descriptor
TI = 0
TI = 1
Cached
Selector
Used If
Available
Segment
Base
Address
Segment
Descriptor
Local Descriptor
Table
Figure 3-7. Selector Mechanism Caching
Revision 1.0
69
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