GX1 Datasheet, PDF (38/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Signal Definitions (Continued)
2.2.4 Video Interface Signals (Continued)
Signal Name
BGA SPGA
Pin No Pin No
Type
FP_HSYNC
L2
R4
O
FP_VSYNC
J1
P2
O
ENA_DISP
AD5
AM6
O
VID_RDY
AD1
AK2
I
VID_VAL
M2
S3
O
VID_DATA[7:0]
Refer
Refer
O
to
to
Table 2-3 Table 2-5
PIXEL[17:0]
Refer
Refer
O
to
to
Table 2-3 Table 2-5
Description
Flat Panel Horizontal Sync
Flat Panel Horizontal Sync establishes the line rate and horizon-
tal retrace interval for a TFT display. Polarity is programmable.
(See Table 4-31 on Page 151 for programming information.)
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal is not connected.
Flat Panel Vertical Sync
Flat Panel Vertical Sync establishes the screen refresh rate and
vertical retrace interval for a TFT display. Polarity is programma-
ble. (See Table 4-31 on Page 152 for programming information.)
This signal is an input to the CS5530. The CS5530 re-drives this
signal to the flat panel.
If no flat panel is used in the system, this signal is not connected.
Display Enable
Display Enable indicates the active display portion of a scan line
to the CS5530.
In a CS5530-based system, this signal is required to be con-
nected.
Video Ready
This input signal indicates that the video FIFO in the CS5530 is
ready to receive more data.
Video Valid
VID_VAL indicates that video data to the CS5530 is valid.
Video Data Bus
When the Video Port is enabled, this bus drives Video (YUV or
RGB 5:6:5) data synchronous to the VID_CLK output.
Graphics Pixel Data Bus
This bus drives graphics pixel data synchronous to the PCLK
output.
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