GX1 Datasheet, PDF (186/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Electrical Specifications (Continued)
6.2 ELECTRICAL CONNECTIONS
6.2.1 Power/Ground Connections and Decoupling
Testing and operating the GX1 processor requires the use
of standard high frequency techniques to reduce parasitic
effects. These effects can be minimized by filtering the DC
power leads with low-inductance decoupling capacitors,
using low-impedance wiring, and by connecting all V_CC2
and V_CC3 pins to the appropriate voltage levels.
6.2.1.1 Power Planes
Figure 6-1 shows layout recommendations for splitting the
power plane between V_CC2 (core: 1.6V, 1.8V, 2.0V) and
V_CC3 (I/O: 3.3V) volts in the BGA package. The illustration
assumes there is one power plane, and no components on
the back of the board.
Figure 6-2 shows layout recommendations for splitting the
power plane between V_CC2 (core: 1.6V, 1.8V, 2.0V) and
V_CC3 (I/O: 3.3V) volts in the SPGA package.
3.3V Plane
(V_CC3)
1
A
26
A
3.3V Plane
(V_CC3)
1.6V, 1.8V, or 2.0V Plane
(V_CC2)
Geode™ GX1
Processor
352 BGA - Top View
1.6V, 1.8V, or 2.0V Plane
(V_CC2)
3.3V Plane
(V_CC3)
AF
1
AF
26
Legend
= High frequency capacitor
= 220 µF, low ESR capacitor
= 3.3V connection
= 1.6V, 1.8V, or 2.0V connection
3.3V Plane
(V_CC3)
Note: Where signals cross plane splits, it is recommended to include
AC decoupling between planes with 47 pF capacitors.
Figure 6-1. BGA Recommended Split Power Plane and Decoupling
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