GX1 Datasheet, PDF (166/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Integrated Functions (Continued)
Table 4-39. Virtual VGA Registers
Bit
Name
Description
GX_BASE+8140h-8143h
GP_VGA_WRITE Register (R/W)
Default Value = xxxxxxxxh
31:28
27:24
23:21
20
19
18:16
15:12
11:8
7:0
RSVD
MAP_MASK
RSVD
W3
W2
RC
SRE
SR
BIT_MASK
Reserved: Set to 0.
Map Mask: Enables planes 3 through 0 for writing. Combined with chain control to determine the
final enables.
Reserved: Set to 0.
Write Mode 3: Selects write mode 3 by using the bit mask with the rotated data.
Write Mode 2: Selects write mode 2 by controlling set/reset.
Rotate Count: Controls the 8-bit rotator.
Set/Reset Enable: Enables the set/reset value for each plane.
Set/Reset: Selects 1 or 0 for each plane if enabled.
Bit Mask: Selects data from the data latches (last read data).
GX_BASE+8144h-8147h
31:18
RSVD
17:16
RMS
15
F15
14
PC4
13
C4
12
PB
11
COE
10
W2
9
R2
8
RM
7:4
CCM
3:0
CC
GP_VGA_READ Register (R/W)
Default Value = 00000000h
Reserved: Set to 0.
Read Map Select: Selects which plane to read in read mode 0 (Chain 2 and Chain 4 inactive).
Force Address Bit 15: Forces address bit 15 to 0.
Packed Chain 4: Provides 64 KB of packed pixel addressing when used with Chain 4 mode. This bit
causes the VGA addresses to be shifted right by 2 bits.
Chain 4 Mode: Selects Chain 4 mode for both read operations and write operations. This overrides
bits 10 and 9 of this register.
Page Bit: Becomes LSB of address if COE is set high.
Chain Odd/Even: Selects PB rather than A0 for least-significant VGA address bit.
Write Chain 2 Mode: Selects Chain 2 mode for write operations. Bit 13 overrides this bit.
Read Chain 2 Mode: Selects Chain 2 mode for read operations. Bit 13 overrides this bit.
Read Mode: Selects between read mode 0 (normal) and read mode 1 (color compare).
Color Compare Mask: Selects planes to include in the color comparison (read mode 1).
Color Compare: Specifies value of each plane for color comparison (read mode 1).
GX_BASE+8210h-8213h
31:14
RSVD
13:8
VGA_RD_BASE
7:6
RSVD
5:0
VGA_WR_BASE
GP_VGA_BASE (R/W)
Default Value = xxxxxxxxh
Reserved: Set to 0.
Read Base Address: The VGA base address is added to the graphics memory base to specify
where VGA memory starts. The VGA base address provides address bits [19:14] when mapping
VGA accesses into graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 4 MB of graphics memory. This register is used for reads to the VGA trace buffer.
Reserved: Set to 0.
Write Base Address: The VGA base address is added to the graphics memory base to specify
where VGA memory starts. The VGA base address provides address bits [19:14] when mapping
VGA accesses into graphics memory. This allows the VGA base address to start on any 64 KB
boundary within the 4 MB of graphics memory. This register is used for writes to the VGA trace buffer.
GX_BASE+8214h-8217h
GP_VGA_LATCH Register (R/W)
Default Value = xxxxxxxxh
31:0
LATCH
Display Latch: Specifies the value in the VGA display latch. VGA read operations cause VGA frame
buffer data to be latched in the display latch. VGA write operations can use the display latch as a
source of data for VGA frame buffer write operations.
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