GX1 Datasheet, PDF (232/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
Table 8-27. Processor Core Instruction Set Summary (Continued)
Flags
Real Prot’d Real Prot’d
Mode Mode Mode Mode
Instruction
SUB Integer Subtract
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
SVDC Save Segment Register and Descriptor
SVLDT Save LDTR and Descriptor
SVTS Save TSR and Descriptor
TEST Test Bits
Register/Memory and Register
Immediate Data and Register/Memory
Immediate Data and Accumulator
VERR Verify Read Access
To Register/Memory
VERW Verify Write Access
To Register/Memory
WAIT Wait Until FPU Not Busy
WBINVD Write-Back and Invalidate Cache
WRMSR Write to Model Specific Register
XADD Exchange and Add
Register1, Register2
Memory, Register
XCHG Exchange
Register/Memory with Register
Register with Accumulator
XLAT Translate Byte
XOR Boolean Exclusive OR
Register to Register
Register to Memory
Memory to Register
Immediate to Register/Memory
Immediate to Accumulator (short form)
Opcode
O D I T S Z A P C Clock Count
F F F F F F F F F (Reg/Cache Hit)
Issues
2 [10dw] [11 reg r/m]
x -- - x x x x x
1
2 [100w] [mod reg r/m]
1
2 [101w] [mod reg r/m]
1
8 [00sw] [mod 101 r/m] ###
1
2 [110w] ###
1
0F 78 [mod sreg3 r/m]
---------
20
0F 7A [mod 000 r/m]
---------
20
0F 7C [mod 000 r/m]
---------
21
8 [010w] [mod reg r/m]
0 -- - x x ux 0
1
F [011w] [mod 000 r/m] ###
1
A [100w] ###
1
0F 00 [mod 100 r/m]
- - - - - x- - -
0F 00 [mod 101 r/m]
9B
0F 09
0F 30
- - - - - x- - -
---------
1
---------
23
---------
0F C[000w] [11 reg2 reg1]
0F C[000w] [mod reg r/m]
x- - - xxxxx
2
2
8[011w] [mod reg r/m]
9[0 reg]
D7
---------
2
2
---------
5
3 [00dw] [11 reg r/m]
0- - - xxux0
1
3 [000w] [mod reg r/m]
1
3 [001w] [mod reg r/m]
1
8 [00sw] [mod 110 r/m] ###
1
3 [010w] ###
1
1
b
h
1
1
1
1
20
s
s
20
s
s
21
s
s
1
b
h
1
1
8
a g,h,j,p
8
a g,h,j,p
1
23
t
t
2
2
2
b,f
f,h
2
5
h
1
b
h
1
1
1
1
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