GX1 Datasheet, PDF (64/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Processor Programming (Continued)
3.4.2 Memory Address Space
The processor directly addresses up to 4 GB of physical
memory even though the memory controller addresses
only 512 MB of DRAM. Memory address space is
accessed as BYTE, WORD (16 bits) or DWORDs (32 bits).
WORD and DWORDs are stored in consecutive memory
bytes with the low-order byte located in the lowest address.
The physical address of a WORD or DWORD is the byte
address of the low-order byte.
The processor allows memory to be addressed using nine
different addressing modes. These addressing modes are
used to calculate an offset address, often referred to as an
effective address. Depending on the operating mode of the
CPU, the offset is then combined, using memory manage-
ment mechanisms, into a physical address that is applied
to the physical memory devices.
Memory management mechanisms consist of segmenta-
tion and paging. Segmentation allows each program to use
several independent, protected address spaces. Paging
translates a logical address into a physical address using
translation lookup tables. Virtual memory is often imple-
mented using paging. Either or both of these mechanisms
can be used for management of the GX1 processor mem-
ory address space.
3.5 OFFSET, SEGMENT, AND PAGING
MECHANISMS
The mapping of address space into a sequence of memory
locations (often cached) is performed by the offset, seg-
ment, and paging mechanisms.
In general, the offset, segment and paging mechanisms
work in tandem as shown below:


instruction offset offset mechanism offset address


offset address segment mechanism linear address


linear address paging mechanism physical page.
As will be explained, the actual operations depend on sev-
eral factors such as the current operating mode and if pag-
ing is enabled.
Note: The paging mechanism uses part of the linear address
as an offset on the physical page.
3.5.1 Offset Mechanism
In all operating modes, the offset mechanism computes an
offset (effective) address by adding together up to three
values: a base, an index and a displacement. The base, if
present, is the value in one of eight general registers at the
time of the execution of the instruction. The index, like the
base, is a value that is contained in one of the general reg-
isters (except the ESP register) when the instruction is exe-
cuted. The index differs from the base in that the index is
first multiplied by a scale factor of 1, 2, 4 or 8 before the
summation is made. The third component added to the
memory address calculation is the displacement that is a
value supplied as part of the instruction. Figure 3-3 illus-
trates the calculation of the offset address.
Nine valid combinations of the base, index, scale factor and
displacement can be used with the CPU instruction set.
These combinations are listed in Table 3-19. The base and
index both refer to contents of a register as indicated by
[Base] and [Index].
In real mode operation, the CPU only addresses the lowest
1 MB of memory and the offset contains 16-bits. In pro-
tected mode the offset contains 32 bits. Initialization and
transition to protected mode is described in Section 3.9.4
“Initialization and Transition to Protected Mode” on page
93.
Base
Index
Displacement
Scaling
x1, x2, x4, x8
+
Offset Address
(Effective Address)
Figure 3-3. Offset Address Calculation
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