GX1 Datasheet, PDF (244/247 Pages) National Semiconductor (TI) – Processor Series Low Power Integrated x86 Solution

Instruction Set (Continued)
8.6 EXTENDED MMX INSTRUCTION SET
National Semiconductor has added instructions to its
implementation of the Intel MMX architecture in order to
facilitate writing of multimedia applications. In general,
these instructions allow more efficient implementation of
multimedia algorithms, or more precision in computation
than can be achieved using the basic set of MMX instruc-
tions. All of the added instructions follow the SIMD (single
instruction, multiple data) format. Many of the instructions
add flexibility to the MMX architecture by allowing both
source operands of an instruction to be preserved, while
the result goes to a separate register that is derived from
the input.
Table 8-33 summarizes the Extended MMX Instructions.
The abbreviations used in the table are listed in Table 8-32.
Configuration control register CCR7(0) at Index EBh (see
Table 3-11 on Page 53) must be set to allow the execution
of the Extended MMX instructions.
Table 8-32. Extend MMX Instruction Set
Table Legend
Abbreviation
Description
<----
[11 mm reg]
mm
reg
<--sat--
<--move--
[byte]
[word]
[dword]
[qword]
[sign xxx]
mm1, mm2
mod r/m
pack
packdw
packwb
Result written.
Binary or binary groups of digits.
One of eight 64-bit MMX registers.
A general purpose register.
If required, the resultant data is saturated to
remain in the associated data range.
Source data is moved to result location.
Eight 8-bit BYTEs are processed in parallel.
Four 16-bit WORDs are processed in
parallel.
Two 32-bit DWORDs are processed in
parallel.
One 64-bit QWORD is processed.
The BYTE, WORD, DWORD or QWORD
most significant bit is a sign bit.
MMX Register 1, MMX Register 2.
Mod and r/m byte encoding (Table 8-15 on
page 217).
Source data is truncated or saturated to
next smaller data size, then concatenated.
Pack two DWORDs from source and two
DWORDs from destination into QWORDs in
destination register.
Pack QWORDs from source and QWORDs
from destination into eight BYTEs in desti-
nation register.
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